GAA Semiconductor Channel Structure for Higher NMOS Mobility
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Solution Overview
Problem
Current semiconductor structures face challenges in improving carrier mobility for both N-type and P-type GAA transistors while maintaining high process compatibility and low process costs, especially in forming Si and SiGe channels.
Innovation Solution
The semiconductor structure includes a substrate with P-type and N-type regions, featuring protrusions with first and second channel structure layers. The first channel layer improves carrier mobility in PMOS transistors, and the second channel layer, comprising a center and sidewall channel film, enhances mobility in NMOS transistors, achieved through specific layer configurations and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around (GAA) transistor structure is adopted to improve channel control capability, then the ability to suppress short-channel effect is improved, but the complexity of device structure increases
Solution Approach 1:
The channel structure is segmented into multiple suspended channel layers (first channel layers for PMOS, second channel layers for NMOS) that are separated and independently configured. This segmentation allows different channel materials and structures for different transistor types while maintaining the GAA architecture's superior channel control capability.
Solution Approach 2:
Different channel structure configurations are applied to different regions: the P-type region receives first channel layers optimized for PMOS transistors, while the N-type region receives second channel layers with center and sidewall films optimized for NMOS transistors. This local quality approach tailors the channel structure to the specific requirements of each transistor type, improving overall device performance while managing structural complexity.
2Reliability
If different channel materials are used to improve carrier mobility in NMOS and PMOS transistors, then the performance of transistors is improved, but the complexity of manufacturing process increases
Solution Approach 1:
The patent applies different channel material compositions to different regions: SiGe channel layers are used in the P-type region for PMOS transistors to enhance hole mobility, while Si-based channel layers with center and sidewall films are used in the N-type region for NMOS transistors to enhance electron mobility. This local differentiation optimizes carrier mobility for each transistor type while using compatible manufacturing processes.
Solution Approach 2:
The channel structure is divided into separate first channel layers for PMOS and second channel layers for NMOS, allowing independent material optimization and process control for each transistor type. This segmentation enables tailored material selection without requiring entirely separate manufacturing lines.
3Reliability
If complex channel structure configurations are implemented to improve transistor performance, then the carrier mobility is improved, but the process cost increases
Solution Approach 1:
The patent merges the formation of first and second channel layers into a unified manufacturing process flow. Both channel structures are formed using similar process steps including deposition of channel materials, formation of sacrificial layers, and selective removal processes. This merging reduces the number of separate process modules needed, thereby lowering overall process costs despite the complexity of the final structure.
Solution Approach 2:
The manufacturing process is designed to be universal, handling both PMOS and NMOS channel formation through the same process equipment and methodology. The process can selectively form different channel structures in different regions using the same toolset, achieving multi-functionality that reduces capital equipment costs and process development expenses.
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The method includes: removing a partial thickness of a first channel layer in an N-type region along a direction parallel to the substrate, to form a first trench, where the first trench is defined by the remaining first channel layer and an adjacent sacrificial layer or by the remaining first channel layer and the adjacent sacrificial layer and a limiting layer; filling the first trench with a sidewall channel film; removing the remaining first channel layer in the N-type region, so that a second trench is defined between the sidewall channel film and the adjacent sacrificial layer or between the sidewall channel film and the adjacent sacrificial layer and the limiting layer; and filling the second trench with a center channel film, where the center channel film and the sidewall channel film are in contact with each other to form a second channel layer, and the second channel layer is configured to improve carrier mobility in a channel of an NMOS transistor. Embodiments of the present disclosure improve performance of a semiconductor structure.