GAA Channel Profile Control for Shorter Effective Channel Length
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Solution Overview
Problem
GAA finFET devices face challenges in achieving lower power consumption, higher performance, and smaller area due to increased gate spacer width, which degrades Ion and device speed, and the trade-off between improving Ion and maintaining effective gate control.
Innovation Solution
The method involves forming channel structures with profile control in GAA FET devices by etching the end portions of the channel structure using hydrogen chloride (HCl), with the profile controlled by etch temperature, pressure, flow rate of HCl, and source material, resulting in V, sigma (Σ), or pi (Π) shapes from a top-down view.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate spacer width is increased to improve gate control, then gate control is improved, but device area increases and device speed decreases
Solution Approach 1:
The channel structure is designed with non-uniform width along its length, creating different local geometries: a first channel section with a first width and a second channel section with a second width. This local variation allows different regions to serve different functions - one region optimized for gate control while another maintains compact area, resolving the contradiction between gate control and device area
Solution Approach 2:
The channel is divided into multiple sections with different width characteristics. The first channel section has a different width than the second channel section, allowing each segment to be optimized independently. This segmentation enables the structure to achieve both good gate control in one region and compact area in another region simultaneously
2Reliability
If the gate spacer width is increased to improve gate control, then gate control is improved, but device speed decreases
Solution Approach 1:
By creating different channel widths in different sections, the invention allows one section to provide strong gate control while the other section maintains high carrier mobility and fast switching. The localized geometric variation ensures that speed-critical regions are not compromised by control-critical regions
Solution Approach 2:
Dividing the channel into sections with different widths allows independent optimization of speed and control characteristics in each segment, enabling the device to achieve both good gate control and high operating speed simultaneously
3Speed
If the effective channel length is reduced to improve device speed, then device speed increases, but gate control deteriorates
Solution Approach 1:
The non-uniform channel width creates regions where the narrower section provides enhanced gate control through stronger electric field coupling, while wider sections maintain low resistance and fast carrier transport. This local differentiation allows short channel length to coexist with effective gate control
Solution Approach 2:
Instead of relying solely on channel length for control, the invention introduces width variation as an additional dimensional parameter. The width modulation provides an alternative mechanism for gate control that is independent of channel length, allowing short channels to achieve good control through width-based field enhancement
4Area of moving object
If the channel structure is scaled down to reduce device area, then device area decreases, but manufacturing complexity increases
Solution Approach 1:
The different channel widths are formed through preliminary patterning and selective etching steps performed before final device assembly. By establishing the width variations early in the fabrication process, the design simplifies subsequent manufacturing steps and reduces overall process complexity despite the compact footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the effective channel length, increases Ion, improves device speed, and reduces resistance between the channel structure and the S/D structure, leading to enhanced device performance by about 5% to 10%.
Implementation Method 1
etching the end portions of the channel structure using hydrogen chloride (HCl), with the profile controlled by etch temperature, pressure, flow rate of HCl
Data Source
AI summary
The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.