GAA Transistor Channel Stacking With Asymmetric Source/Drain Epitaxy
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues in achieving reliable transistor structures and efficient manufacturing.
Innovation Solution
The use of gate all around (GAA) transistor structures with dual-channel number configurations, where one region has fewer semiconductor channel layers than the other, and varying depths of source/drain epitaxy structures, along with specific deposition and etching processes, to improve device performance and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs decrease, but fabrication process difficulty increases and device reliability deteriorates
Solution Approach 1:
The patent divides the semiconductor device into multiple regions with different numbers of semiconductor channel layers (first region with first number of layers, second region with second number of layers). This segmentation allows each region to be optimized independently for its specific function, enabling reliable device operation at scaled dimensions by distributing functionality across multiple specialized zones rather than requiring uniform scaling throughout the entire device.
Solution Approach 2:
The patent implements local quality by creating regions with different numbers of semiconductor channel layers and varying depths of source/drain epitaxy structures. Each region is locally optimized with specific layer counts and depths tailored to its functional requirements, allowing critical areas to maintain higher reliability while other areas support overall device density and performance.
2Productivity
If feature sizes continue to decrease to increase functional density, then more devices fit per chip area, but fabrication process complexity increases
Solution Approach 1:
The patent segments the device into multiple regions with different channel layer configurations, allowing the fabrication process to be broken into manageable stages. Each region can be formed and modified independently through selective etching and epitaxy processes, reducing the overall process complexity compared to attempting to uniformly scale the entire device structure.
Solution Approach 2:
The patent resolves fabrication complexity by transitioning from two-dimensional planar scaling to three-dimensional vertical structuring with multiple semiconductor channel layers. This dimensional change allows functional density to increase through vertical stacking rather than horizontal compression, simplifying the fabrication process while achieving higher device density.
3Ease of manufacture
If uniform semiconductor layer structures are used across all regions, then manufacturing is simpler, but power saving and device control are reduced
Solution Approach 1:
The patent applies local quality by configuring different numbers of semiconductor channel layers in different regions (first region with first number, second region with second number). This allows each region to be optimized for its specific functional requirements, enabling power saving in less critical regions while maintaining high performance in critical regions, thereby reducing overall power consumption while preserving manufacturing feasibility through systematic regional differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved power saving and device control by optimizing the number and depth of semiconductor layers and epitaxy structures, enhancing the reliability and efficiency of semiconductor device fabrication.
Implementation Method 1
forming a first source/drain epitaxy structure in the first recess and a second source/drain epitaxy structure in the second recess
Implementation Method 2
etching, by using the first and second gate structures as etch masks, the first semiconductor layers and the second semiconductor layers to form a first recess within the first semiconductor layers and a second recess within the second semiconductor layers
Data Source
AI summary
A method includes forming first and second semiconductor layers, in which a number of the first semiconductor layers is less than a number of the second semiconductor layers.Embodiments includes etching first and second semiconductor layers to form a first recess within the first semiconductor layers and a second recess within the second semiconductor layers; performing an etching process to deepen the second recess; and forming a first and second source/drain epitaxy structures in the first recess and the deepened second recess. Embodiments also includes after the first and second recesses are formed, performing a first deposition process to form first and second epitaxy layers in the first and second recesses, respectively; performing a second deposition process to form a third epitaxy layer over the first epitaxy layer; and performing a third deposition process to form fourth and fifth epitaxy layers over the third and second epitaxy layers, respectively.