GAA Channel Orientation to Reduce Atomic Step Scattering
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Solution Overview
Problem
The scaling down of semiconductor devices leads to increased complexity and reduced carrier mobility due to atomic steps on silicon substrates, which affects the performance of multi-gate transistors like GAA transistors, as the reduced dimensions exacerbate charge carrier scattering.
Innovation Solution
A method is introduced to fabricate semiconductor devices by aligning the active regions perpendicular to the atomic step propagation direction, utilizing the terrace direction for channel members to minimize carrier scattering, which involves determining the atomic step structure and adjusting the channel member thickness to maintain a ratio below a certain threshold, thereby enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel members are scaled down to reduced dimensions, then device density and integration are improved, but carrier mobility deteriorates due to increased scattering from atomic steps
Solution Approach 1:
The patent applies local quality by orienting channel members specifically along the <110> crystallographic direction where atomic steps are minimized, rather than uniformly in all directions. This directional specificity creates a localized favorable environment for carrier transport in the critical channel region, reducing scattering effects precisely where needed while maintaining overall device density improvements from scaling.
Solution Approach 2:
The patent changes the crystallographic orientation parameter of channel members from conventional directions to specifically the <110> direction. This parameter change fundamentally alters the interaction between charge carriers and atomic step structures, transforming the scattering landscape and improving carrier mobility while preserving the benefits of reduced channel dimensions for device scaling.
2Ease of manufacture
If conventional multi-gate structures are used, then device performance is adequate for general purposes, but performance is insufficient when atomic step scattering is significant in reduced dimensions
Solution Approach 1:
The patent introduces a directional quality distinction by orienting channel members along <110> directions while maintaining conventional multi-gate structures elsewhere. This selective orientation creates local performance enhancement in the channel region without requiring fundamental changes to the overall device architecture or fabrication process, thus maintaining ease of manufacture while improving performance.
Solution Approach 2:
The patent introduces asymmetry in crystallographic orientation, specifically aligning channel members along <110> directions rather than using symmetric <100> orientations. This asymmetric orientation exploits the anisotropic nature of atomic step formation on silicon surfaces, creating preferential pathways for carrier transport that are less susceptible to scattering, thereby enhancing performance without complicating the manufacturing process.
Data Source
AI summary
A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.