GAA Channel Structure for Current Spreading and Strain Control
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Solution Overview
Problem
Existing multi-gate devices, particularly GAA transistors, face challenges such as current crowding at the lightly-doped drain region, poor strain efficiency from the source/drain region to the channel region, and non-uniform layer thicknesses, which degrade device performance and reliability.
Innovation Solution
The fabrication method involves forming an H-shaped or dog-boned shaped semiconductor channel layer with a thicker dummy layer to facilitate removal during the replacement gate process, using a silicon cap layer to prevent spacer and source/drain damage, and maintaining a thin sheet height structure to improve uniformity and strain efficiency, thereby reducing resistances and enhancing short-channel control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional GAA transistor structure is used, then gate control is improved, but current crowding occurs at the lightly-doped drain region and strain efficiency deteriorates
Solution Approach 1:
The patent applies local quality by creating an H-shaped or dog-boned shaped semiconductor channel layer with varying thickness. The channel layer is thicker at the source/drain regions and thinner at the gate region, allowing different local properties: thicker regions provide better current spreading and strain efficiency, while thinner regions maintain gate control and reduce short-channel effects.
2Reliability
If the semiconductor channel layer is made thin to improve short-channel control, then gate control is enhanced, but layer thickness uniformity becomes difficult to maintain
Solution Approach 1:
The patent segments the semiconductor channel layer into regions of different thicknesses (H-shaped or dog-boned configuration). This segmentation allows the channel to have thinner portions under the gate for better control while maintaining thicker portions at the source/drain for improved current spreading and strain efficiency, thus resolving the contradiction between thinness for control and uniformity for manufacturability.
3Ease of manufacture
If a thicker dummy layer is used to facilitate removal during replacement gate process, then manufacturing ease is improved, but device complexity increases
Solution Approach 1:
The patent incorporates a dummy layer within the semiconductor channel stack before gate formation. This preliminary action facilitates subsequent processing steps, particularly the replacement gate process, by providing a sacrificial layer that can be selectively removed to allow gate material deposition. The dummy layer is strategically positioned and sized to enable easy removal while maintaining the desired H-shaped or dog-boned channel profile.
Data Source
AI summary
A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.