Gate-All-Around Channel Thickness Tuning for CMOS Speed Balance
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Solution Overview
Problem
The challenge in the IC industry is to maintain performance and control while scaling down IC technologies, particularly for GAA devices, which face degradation due to differing channel requirements of NMOS and PMOS devices.
Innovation Solution
The solution involves forming GAA transistors with different channel member thicknesses in separate regions of the IC chip by implanting different dopants and performing an etching process, allowing for balanced performance between NMOS and PMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GAA devices are scaled down to improve production efficiency and lower costs, then IC dimensions are reduced, but channel control and performance degrade due to differing channel requirements of NMOS and PMOS devices
Solution Approach 1:
The patent applies local quality by forming first channel members with a first thickness in a first region (for NMOS devices) and second channel members with a second thickness in a second region (for PMOS devices). This allows each region to have optimized channel thickness tailored to its specific device type, improving channel control and performance while maintaining scaled dimensions for high productivity.
2Reliability
If different channel thicknesses are formed for NMOS and PMOS devices to improve performance, then channel control is optimized, but device complexity increases
Solution Approach 1:
The patent segments the substrate into multiple regions (first region for NMOS, second region for PMOS) and forms channel members with different thicknesses in each segment. This segmentation allows independent optimization of channel thickness for each device type, improving performance while managing complexity through regional differentiation rather than complex global processing.
Solution Approach 2:
The patent changes the thickness parameter of channel members based on device type requirements. By forming first channel members with a first thickness and second channel members with a second thickness, the patent optimizes electrical performance parameters for both NMOS and PMOS devices without requiring fundamentally different manufacturing approaches.
3Speed
If channel member thickness is varied to balance drain-induced barrier lowering and drive current, then speed performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by specifying different channel member thicknesses for different device regions: first channel members with thickness between 3-7 nm for NMOS devices and second channel members with thickness between 7-15 nm for PMOS devices. This localized thickness control optimizes the balance between drain-induced barrier lowering and drive current for each device type, improving speed performance with region-specific precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the speed performance of CMOS devices by balancing drain-induced barrier lowering and effective drive current, while maintaining control over channel thickness without affecting device height.
Implementation Method 1
implanting different dopants and performing an etching process
Implementation Method 2
performing an etching process
Data Source
AI summary
A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.