GAA Nanostructure Channel Stack for Precise Threshold Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in size and increase in complexity, there is a need for advanced manufacturing methods that can efficiently form high-performance transistors with precise control over channel regions and source/drain features.
Innovation Solution
The method involves forming an epitaxial stack with alternating layers of SiGe and silicon, patterning fin elements, and using a gate-all-around (GAA) transistor structure. This includes forming a dummy gate stack, oxidizing the first epitaxial layers, removing the oxidized layers from source/drain regions, and growing epitaxial source/drain features. Additionally, high-k dielectric layers and metal gate electrodes are formed to achieve desired work functions for n-type and p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down to increase integration density, then productivity and device complexity are improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The channel region is segmented into multiple thin semiconductor layers (e.g., five 2nm layers totaling 10nm thickness) rather than using a single thick layer. This segmentation enables precise control of the effective channel thickness while maintaining manufacturing feasibility, as each thin layer can be formed with standard epitaxial growth processes.
Solution Approach 2:
The invention transitions from controlling channel thickness in a single dimension to controlling the number and thickness of multiple layers in the vertical dimension. By stacking multiple thin layers, the effective channel thickness is precisely controlled through layer count rather than relying solely on single-layer thickness control, which becomes increasingly difficult at scaled dimensions.
2Productivity
If transistor size is scaled down to increase integration density, then productivity is improved, but device reliability deteriorates
Solution Approach 1:
Different regions of the channel have different local qualities through the use of semiconductor layers with varying bandgaps. The first and second semiconductor layers have different bandgaps, creating localized regions with different electrical properties. This allows optimization of carrier transport in specific regions while maintaining overall device reliability.
Solution Approach 2:
The channel region is constructed as a composite structure with multiple semiconductor layers of different materials (different bandgaps) rather than a uniform material. This composite structure enables simultaneous optimization of different device parameters (carrier mobility, threshold voltage, leakage control) in different layers, improving overall device reliability at scaled dimensions.
3Reliability
If advanced GAA transistor structure is formed with multiple epitaxial layers, then carrier mobility and device performance are improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor layers are pre-formed with different bandgaps during the epitaxial growth process before any gate or contact formation. The alternating n-type and p-type doped layers are created in advance with specific bandgap configurations, establishing the carrier transport pathways before subsequent processing steps. This preliminary structuring simplifies later fabrication steps.
Solution Approach 2:
The invention controls the bandgap parameter of the semiconductor layers to optimize device performance. By selecting materials with specific bandgaps for the first and second semiconductor layers, the carrier mobility and threshold voltage are tuned during the epitaxial growth process itself, rather than requiring complex post-fabrication adjustments.
4Adaptability or versatility
If different threshold voltages are achieved by adjusting gate stack work function, then device versatility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The work function of the gate stack is controlled by adjusting the bandgap parameter of the underlying semiconductor layers. By changing the material composition and bandgap of the first and second semiconductor layers, the effective work function is tuned, which directly controls the threshold voltage. This parameter-based control during epitaxial growth is more precise and manufacturable than post-fabrication work function adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-performance GAA transistors with improved carrier mobility and device performance, while also allowing for the achievement of different threshold voltages by adjusting the work function of the gate stacks.
Implementation Method 1
oxidizing the first epitaxial layers, removing the oxidized layers from source/drain regions
Implementation Method 2
growing epitaxial source/drain features
Data Source
AI summary
A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.