GAA Channel Width Modulation Using Dummy Epitaxy Height Control

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Solution Overview

Problem

Existing technologies face challenges in fabricating Gate-All-Around (GAA) transistors with varying effective channel widths while maintaining a uniform device footprint, particularly when the active region has a small width, making it difficult to form inner spacer features and source/drain features.

Innovation Solution

The approach involves displacing top channel members by a helmet layer and controlling the height of a dummy epitaxial layer and insulator below the source/drain feature to adjust the effective channel width, thereby offering both high performance and low power transistors by varying the number of available channel members in GAA transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the active region width is reduced to maintain uniform device footprint, then device integration density is improved, but the ability to form inner spacer features and source/drain features deteriorates

Engineering Contradiction:
Improvedevice footprintVSAvoidformation of inner spacer features and source/drain features
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent introduces a vertical dimension solution by forming inner spacer features at different heights above the channel structure. Instead of trying to form all features in the same lateral plane, the invention uses vertical stacking to create inner spacers that extend upward from the channel, allowing source/drain features to be formed without lateral overlap conflicts. This dimensional transition resolves the manufacturing difficulty caused by reduced active region width.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of channel members is varied to modulate effective channel width, then transistor performance adaptability is improved, but device structural complexity increases

Engineering Contradiction:
Improvetransistor performance adaptabilityVSAvoiddevice structural complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the channel structure into multiple discrete channel members (e.g., nanowires or nanosheets) that can be selectively removed or retained. By dividing the channel into individual members, the invention enables independent control of each channel's contribution to the effective channel width. This segmentation allows flexible modulation of transistor performance by removing specific channel members while maintaining a standardized overall device structure, thus achieving adaptability without proportionally increasing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary patterning and selective removal of channel members before final device assembly. By pre-defining which channel members will be retained or removed through selective etching or masking processes, the invention simplifies subsequent manufacturing steps. This preliminary action allows the device structure to be prepared in advance with the correct number of active channels, reducing the complexity of later assembly and integration steps.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240339531A1Channel width modulation
Publication Date: 2024.10.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240339531A1 patent drawing
  • US20240339531A1 patent drawing
  • US20240339531A1 patent drawing

AI summary

A semiconductor device according to the present disclosure includes a first base fin and a second base fin extending from a substrate, an isolation feature disposed between the first base fin and the second base fin, a first dummy epitaxial layer disposed on the first base fin, a second dummy epitaxial layer disposed on the second base fin, a first insulator layer over the first dummy epitaxial layer, a second insulator layer over the second dummy epitaxial layer, a first source/drain feature disposed on the first insulator layer, a second source/drain feature disposed on the second insulator layer. A thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin.