Horizontal Gate-All-Around Channels With Uniform Wire Thickness
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Solution Overview
Problem
The challenge in semiconductor processing is achieving consistent and repeatable performance in nanometer-scale features of VLSI and ULSI devices due to significant variations in the thickness of silicon, silicon germanium, high k value dielectric, and work function tuning layers, leading to undesirable electrical performance and repeatability in horizontal all around gate structures.
Innovation Solution
A method involving the formation of superlattices with alternating semiconductor and sacrificial material layers, followed by selective etching and capping layer deposition, where the etching process conditions are adjusted to achieve uniform trimmed thicknesses and spacings between semiconductor layers, and the capping layer thicknesses are measured and adjusted to minimize variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard epitaxial growth and trimming processes are used to form horizontal all around gate structures, then the manufacturing process can be completed, but significant variations in layer thickness and spacing occur leading to poor device performance repeatability
Solution Approach 1:
The patent applies preliminary action by forming superlattice structures with alternating semiconductor and sacrificial material layers before the final channel formation. The sacrificial layers are strategically positioned to control subsequent trimming operations, ensuring uniform channel thickness and spacing. This preliminary structuring enables precise control over final device dimensions that cannot be achieved through standard single-layer epitaxial growth alone.
Solution Approach 2:
The patent employs parameter changes by varying the thickness of alternating layers in the superlattice structure during epitaxial growth. By controlling the relative thicknesses of semiconductor versus sacrificial material layers, the process optimizes both the initial structure formation and the subsequent selective removal steps, achieving uniform final channel dimensions despite variations in standard trimming processes.
2Manufacturing precision
If alternating layers of semiconductor and sacrificial material are formed to create superlattice structures, then channel uniformity can be improved, but the device structure and processing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the channel formation process into distinct stages through the superlattice structure. The alternating semiconductor and sacrificial layers create discrete segments that can be selectively removed, allowing independent control over channel thickness and spacing. This segmentation transforms a single complex trimming operation into multiple controlled removal steps, improving precision despite increased structural complexity.
Solution Approach 2:
The sacrificial material layers serve as intermediaries in the channel formation process. These temporary structures enable precise control during manufacturing by acting as spacers and thickness references during epitaxial growth, then being selectively removed to define final channel dimensions. The intermediaries facilitate uniform channel formation without requiring direct manipulation of the final channel structure during critical growth phases.
3Manufacturing precision
If selective etching is used to remove sacrificial material and trim semiconductor layers, then layer spacing and thickness can be controlled, but process complexity and number of steps increases
Solution Approach 1:
The patent applies the taking out principle by selectively removing the sacrificial material layers from the superlattice structure through selective etching. This extraction of intermediate elements enables precise definition of channel spacing and thickness, as the removed sacrificial layers leave behind uniformly spaced semiconductor channels. The selective removal process transforms the complex multi-layer structure into the simpler final device architecture with controlled dimensions.
Solution Approach 2:
The selective etching process applies preliminary action by pre-defining the final channel dimensions through controlled removal of sacrificial material before subsequent processing steps. The etching process establishes uniform spacing and thickness references that guide later manufacturing operations, ensuring consistent channel geometry throughout the device structure without requiring continuous adjustment in subsequent steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform spacings and thicknesses of the final semiconductor wires, enhancing the repeatability and performance of the semiconductor devices by reducing variations in layer thickness and spacing, thereby improving the electrical performance of horizontal gate all around field effect transistors.
Implementation Method 1
The semiconductor channels are configured in part by epitaxially forming a plurality of alternating layers of the semiconductor material and a sacrificial material to form a superlattice structure
Implementation Method 2
The sacrificial material is removed to leave behind individual lengths of the semiconductor material which will form individual channels
Implementation Method 3
these individual lengths or wires of the semiconductor material are then trimmed to the desired channel length, which also results in removal of a portion of each wire on the other surfaces thereof
Implementation Method 4
A capping layer, for example an additional semiconductor layer is then formed on each wire
Data Source
AI summary
A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.