GAA Transistor Cladding Structure for Source/Drain Epitaxy
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Solution Overview
Problem
In existing semiconductor technologies, the performance of gate-all-around (GAA) transistors is adversely impacted due to limited contact area for epitaxially growing source/drain structures as channel layer dimensions shrink, and the extension of gate structures along cut active structures can lead to inactive gate formations that do not serve as active gate structures.
Innovation Solution
The method involves forming a semiconductor cladding layer that extends along the cut edge of channel layers, allowing for the formation of dummy gate structures and source/drain recesses with asymmetric sidewalls, which increases the contact area for epitaxial growth of the source/drain structures, thereby improving the growth process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel layer dimensions are reduced to increase integration density, then more components can be integrated into a given area, but the contact area for epitaxially growing source/drain structures becomes limited
Solution Approach 1:
The patent introduces a semiconductor cladding layer that extends along the sidewalls of the channel layers in the vertical dimension, creating an asymmetric source/drain recess. This dimensional extension provides additional epitaxial growth surface area without increasing the planar footprint, thereby maintaining integration density while increasing the contact area for source/drain structure formation.
Solution Approach 2:
The patent creates an asymmetric source/drain recess by forming a semiconductor cladding layer that extends along only one sidewall of the channel layers. This asymmetric structure provides unequal contact areas on either side of the channel, enabling improved epitaxial growth of source/drain structures while maintaining compact device dimensions for high integration density.
2Reliability
If gate structures are extended along cut active structures to maintain continuity, then gate coverage is improved, but inactive gate structures are formed that do not serve as active gate structures
Solution Approach 1:
The patent applies different properties to different regions by forming a semiconductor cladding layer that extends along the sidewall of channel layers adjacent to the cut edge. This local modification creates a distinguished region that enables proper active gate formation without extending inactive gate structures into non-functional areas, thereby maintaining gate coverage where needed while avoiding unnecessary complexity.
3Ease of manufacture
If symmetric source/drain recesses are formed in conventional GAA transistors, then manufacturing simplicity is maintained, but the contact area for epitaxial growth is limited
Solution Approach 1:
The patent intentionally introduces asymmetry by forming a semiconductor cladding layer that extends along one sidewall of the channel layers but not the other. This asymmetric configuration increases the contact area for epitaxial growth of source/drain structures while adding minimal manufacturing complexity, as it only requires selective deposition on one side during the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the contact area for epitaxial growth of source/drain structures, improving the performance of GAA transistors by increasing the available contact area and avoiding issues related to limited growth space and inactive gate structures.
Implementation Method 1
limited contact area for epitaxially growing source/drain structures
Data Source
AI summary
A semiconductor device includes an active gate structure extending along a first lateral direction. The semiconductor device includes an inactive gate structure also extending along the first lateral direction. The semiconductor device includes a first epitaxial structure disposed between the active gate structure and the inactive gate structure along a second lateral direction perpendicular to the first lateral direction. The active gate structure wraps around each of a plurality of channel layers that extend along the second direction, and the inactive gate structure straddles a semiconductor cladding layer that continuously extends along a first sidewall of the first epitaxial structure and across the plurality of channel layers.