GAA CMOS Channel Materials for p-Type Mobility Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate-all-around (GAA) devices with silicon channels for both n-type and p-type transistors face performance degradation due to shared material, necessitating improved channel materials for enhanced mobility and transconductance.
Innovation Solution
The fabrication of CMOS GAA devices involves forming p-type transistors with silicon germanium (SiGe) channels and n-type transistors with silicon (Si) channels, using integrated processes that alternate SiGe and Si layers, allowing for selective removal of materials during channel formation to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon channels are used for both n-type and p-type GAA transistors, then fabrication process simplicity is maintained, but p-type transistor performance is degraded
Solution Approach 1:
The patent applies local quality by using different semiconductor materials for different transistor types: silicon channels for n-type GAA transistors and silicon germanium channels for p-type GAA transistors. This allows each transistor type to have optimized material properties locally, improving p-type transistor performance while maintaining separate fabrication processes for each material type.
Solution Approach 2:
The fabrication process is segmented into separate sequences: one for forming silicon channels in n-type regions and another for forming silicon germanium channels in p-type regions. This segmentation allows independent optimization of materials and processes for each transistor type, resolving the contradiction between process simplicity and performance.
2Reliability
If different semiconductor materials are used for n-type and p-type GAA transistor channels, then transistor performance is improved, but fabrication process complexity increases
Solution Approach 1:
Different semiconductor materials are applied locally to specific transistor regions: silicon for n-type and silicon germanium for p-type. This enables performance optimization for each transistor type by selecting materials with appropriate electrical properties, while the fabrication process manages complexity through region-specific processing sequences.
Solution Approach 2:
The patent changes material composition parameters to optimize transistor performance. Silicon germanium with varying germanium concentrations is used for p-type transistors to achieve desired hole mobility and threshold voltage characteristics, while pure silicon is used for n-type transistors. This parameter variation allows performance improvement despite increased fabrication complexity.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first semiconductor layer including a first semiconductor material in a first area of a substrate; alternately depositing second semiconductor layers and third semiconductor layers over the first semiconductor layer and over the substrate to form a semiconductor layer stack, wherein the second semiconductor layers include a second semiconductor material, the third semiconductor layers include the first semiconductor material, the second semiconductor material is different from the first semiconductor material, and a bottom surface of one of the second semiconductor layers contacts the first semiconductor layer in the first area and contacts the substrate in a second area of the substrate; planarizing a top surface of the semiconductor layer stack; and patterning the semiconductor layer stack to form a first semiconductor structure in the first area and a second semiconductor structure in the second area.