Adjacent GAA CMOS Source/Drain Layout for Epitaxy Isolation
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Solution Overview
Problem
The formation of gate-all-around (GAA) transistor devices faces challenges in preventing epitaxial growth of PMOS source and drain regions on NMOS devices and vice versa, leading to contamination issues and performance degradation due to residual dielectric material remnants on nanoribbons.
Innovation Solution
A method is developed to form integrated circuits with laterally adjacent PMOS and NMOS devices, where inner spacers and source/drain regions are created with precise width control, using dielectric layers to prevent contamination, and employing a mask protection scheme to isolate the devices during processing, allowing for the formation of epitaxial regions without foreign material contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial growth is used to form source and drain regions in laterally adjacent PMOS and NMOS devices, then the source and drain regions can be formed with good crystal structure, but unwanted epitaxial growth occurs on adjacent devices causing contamination
Solution Approach 1:
The patent divides the formation process into separate sequential steps for PMOS and NMOS devices. First, PMOS inner spacers and source/drain regions are formed while the NMOS device is protected by a mask. Then, the mask is removed and NMOS inner spacers and source/drain regions are formed while the PMOS device is protected. This segmentation prevents cross-contamination during epitaxial growth.
Solution Approach 2:
The patent applies preliminary protective action by forming a mask over the NMOS device before initiating epitaxial growth for PMOS source and drain regions. This preliminary protection prevents unwanted epitaxial growth on the NMOS device. Similarly, a mask is applied to PMOS before NMOS epitaxial growth.
2Reliability
If dielectric material is used during source and drain formation, then device isolation and protection are achieved, but residual dielectric remnants remain on nanoribbons causing performance degradation
Solution Approach 1:
The patent extracts and removes the dielectric material after it has served its protective function during epitaxial growth. The inner spacers comprising dielectric material are removed after the source and drain regions are formed, eliminating residual dielectric remnants that would otherwise contaminate the nanoribbons and degrade device performance.
Solution Approach 2:
The dielectric material serving as inner spacers is discarded after fulfilling its protective role during epitaxial growth. The removal of these spacers eliminates contamination sources while the source and drain regions formed during this process are recovered as functional structures.
3Productivity
If simultaneous formation of source and drain regions is attempted, then processing time is reduced, but contamination between adjacent PMOS and NMOS devices occurs
Solution Approach 1:
The patent segments the source and drain formation process into two separate sequential operations: first forming PMOS regions with NMOS protected by a mask, then forming NMOS regions with PMOS protected. This segmentation prevents contamination while maintaining reasonable processing efficiency.
Solution Approach 2:
The patent applies preliminary masking protection to one device type before forming source and drain regions in the other device type. This preliminary action prevents cross-contamination during epitaxial growth while allowing efficient sequential processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of GAA transistor devices by preventing unwanted epitaxial growth and reducing contamination, thereby improving the accuracy and reliability of source and drain region formation.
Implementation Method 1
using dielectric layers to prevent contamination
Implementation Method 2
employing a mask protection scheme to isolate the devices during processing
Implementation Method 3
preventing epitaxial growth of PMOS source and drain regions on NMOS devices
Data Source
AI summary
An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure