Gate-All-Around Common Metal Gates With Dual Dipole Threshold Tuning
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Solution Overview
Problem
The scaling of multi-gate transistors, such as tri-gate transistors, faces challenges in maintaining mobility improvement and short channel control as device dimensions shrink below the 10 nanometer node, particularly due to the trade-off between feature dimension and spacing, and the complexity of lithographic processes, which is exacerbated by the use of dual metal gate flows in gate-all-around architectures.
Innovation Solution
Implementing a common metal gate approach with differentiated dipole layers and an additive selective metal gate patterning process, using a blanket seed liner and carbon-based hardmask, to achieve tight N-P boundaries and high transistor density, reducing the number of masks and etch operations, and enabling a mid-gap metal gate stack with dual polarity dipoles for multi-VT devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual metal gate flows are used in gate-all-around architectures, then device performance can be optimized, but process complexity and lithographic constraints increase significantly
Solution Approach 1:
The patent merges the patterning of N-type and P-type metal gates into a single lithographic step using a common etch process. The gate dielectric stack with differentiated dipole layers serves as a unified mask structure that enables selective metal gate formation without requiring separate lithographic patterns for N and P regions, thereby reducing process complexity while maintaining device performance
Solution Approach 2:
The gate dielectric is segmented into multiple layers with different dipole moments oriented perpendicular to the substrate. This segmentation allows each layer to contribute differently to the threshold voltage control of N-type and P-type devices, enabling dual metal gate functionality through a single patterned structure rather than requiring complex dual-patterning processes
2Productivity
If feature dimensions are reduced below 10 nanometer node, then transistor density increases, but maintaining short channel control and mobility improvement becomes more difficult
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional gate-all-around control by wrapping the metal gate structure completely around the nanowire channel. This dimensional change provides superior electrostatic control over the channel at sub-10nm scales, maintaining short channel control and mobility improvement while enabling higher transistor density through vertical stacking
3Ease of manufacture
If the number of masks and etch operations is reduced, then manufacturing cost and process complexity decrease, but achieving tight N-P boundaries and high transistor density becomes more challenging
Solution Approach 1:
The patent applies local quality by creating gate dielectric stacks with different dipole layer configurations in specific regions corresponding to N-type and P-type devices. The differentiated dipole layers are positioned locally to provide the correct threshold voltage adjustment for each device type, while the overall structure is formed through a single lithographic pattern that maintains tight N-P boundaries
Data Source
AI summary
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.