GAA Source/Drain Contact Layout to Cut Gate Parasitic Capacitance
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Solution Overview
Problem
The presence of parasitic capacitance between gates and dummy metal lines in semiconductor devices decreases device performance, particularly in gate all around (GAA) transistor structures, due to the inefficiencies in the current source/drain contact formation processes.
Innovation Solution
The dummy metal lines are replaced with a dielectric material to eliminate parasitic capacitance, and the process involves forming epitaxial source/drain structures, gate dielectric layers, and conductive contacts, with specific etching and deposition techniques to create a semiconductor device structure that reduces capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy metal lines are used in semiconductor devices, then electrical connectivity is provided, but parasitic capacitance increases which decreases device performance
Solution Approach 1:
The patent removes the harmful dummy metal lines from the semiconductor device structure and replaces them with dielectric material. This extraction of the problematic element (dummy metal lines that generate parasitic capacitance) directly resolves the contradiction by eliminating the source of harmful electrical interactions while maintaining the structural integrity and electrical connectivity through alternative means.
Solution Approach 2:
The patent changes the material parameter of the dummy structures from conductive metal to insulating dielectric material. This parameter change fundamentally alters the electrical characteristics, eliminating parasitic capacitance generation while maintaining the mechanical and structural functions that dummy lines previously served in the semiconductor device.
2Ease of manufacture
If conventional current source/drain contact formation processes are used, then manufacturing is simplified, but parasitic capacitance between gates and dummy metal lines increases
Solution Approach 1:
The patent converts the previously harmful dummy metal lines into beneficial dielectric structures. By replacing conductive material with insulating material in the dummy line positions, the structure that previously generated parasitic capacitance now serves as a beneficial insulating element that eliminates electrical interference while maintaining structural support and process compatibility.
Data Source
AI summary
A semiconductor device comprises semiconductor layers extending over a substrate, a gate structure, gate spacers, epitaxial source/drain structures, a conductive contact and a lower dielectric plug. The gate structure wraps around the semiconductor layers. The gate spacers are on opposite sidewalls of the gate structure. The epitaxial source/drain structures are on opposite sides of the metal gate structure. The conductive contact is over a first one of the epitaxial source/drain structures. The lower dielectric plug is over a second one of epitaxial source/drain structures, wherein from a cross-sectional view, the gate spacers are between the lower dielectric plug and the conductive contact, wherein from a plan view, the lower dielectric plug and the conductive contact have a same pattern.