GAA Semiconductor Contact Layout for Lower IR Drop
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistors in semiconductor manufacturing is challenging due to complexity in fabricating the GAA features around nanowires, and there is a need for improved methods to enhance gate control and reduce short-channel effects while maintaining scalability and performance.
Innovation Solution
A semiconductor structure is designed with high-density and high-speed circuits in separate cell regions, utilizing parallel and series connections for drain-node contact plugs to reduce IR voltage drop and optimize component density and performance, incorporating multi-patterning processes for precise feature formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA features are fabricated around nanowires using conventional processes, then gate control is improved and short-channel effects are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct components: nanowire channels, gate electrodes wrapping around the nanowires, and separate source/drain regions. This segmentation allows each component to be optimized independently while maintaining overall device performance and simplifying the fabrication process through modular assembly
Solution Approach 2:
The gate electrode is designed to wrap around and surround the nanowire channel in a nested configuration, with the gate enclosing the channel on multiple sides. This nested structure provides comprehensive gate control over the channel while maintaining a compact footprint that simplifies integration into standard CMOS processes
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing complexity increases
Solution Approach 1:
The GAA transistor structure is designed to be compatible with standard CMOS fabrication processes, allowing the same process toolkit to be used for both conventional planar transistors and the new GAA structures. This universality enables scaling down device dimensions without requiring entirely new manufacturing equipment or processes, thereby maintaining productivity while achieving advanced node fabrication
3Quantity of substance
If drain-node contact plugs use series connections, then component density increases, but IR voltage drop increases
Solution Approach 1:
The patent transitions from two-dimensional planar contact arrangements to three-dimensional vertical stacking of contact plugs. By stacking contact plugs vertically across multiple metal layers, the design achieves higher component density in the vertical dimension while maintaining low resistance through direct vertical pathways that minimize current flow distance and reduce IR voltage drop
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first circuit in a first cell region, a first contact plug, a first metal layer and a second metal layer. The first circuit includes a first n-type nanostructure transistor and a first p-type nanostructure transistor. The first contact plug is electrically connected to drain nodes of the first n-type nanostructure transistor and the first p-type nanostructure transistor. The first metal layer is over the first contact plug, and includes a first line and a second line electrically connected to the first contact plug. The second metal layer is over the first metal layer, and includes a third line electrically connected to both the first line and the second line.