GAA Transistor Contact Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit (IC) technologies progress towards smaller technology nodes, existing contact features for source/drain in gate-all-around (GAA) transistors impact isolation margin and cost, limiting the performance and reliability of circuit cells.
Innovation Solution
The implementation of non-self-aligned source/drain contacts with varying widths, which are separated from the gate spacers, reduces contact-to-gate parasitic capacitance and allows for larger contact sizes without compromising isolation margins, thereby improving cell performance and reducing processing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing contact features for source/drain in GAA transistors are used, then manufacturing process is simpler, but isolation margin deteriorates and cost increases
Solution Approach 1:
The contact feature is segmented into two distinct parts: a first contact feature for the source region and a second contact feature for the drain region. These segmented contacts are positioned at different locations relative to the gate structure, allowing independent optimization of each contact's dimensions and positioning to improve isolation margin while maintaining manufacturing feasibility
Solution Approach 2:
Different contact features are assigned different local qualities through varying their widths and positions. The first contact feature has different dimensions than the second contact feature, allowing each to be optimized for its specific functional requirement - this local differentiation improves overall isolation margin without requiring complete restructuring of all contacts
2Reliability
If non-self-aligned source/drain contacts with varying widths are implemented, then contact-to-gate parasitic capacitance is reduced and isolation margin is maintained, but manufacturing precision requirements increase
Solution Approach 1:
Gate spacers are formed first as a preliminary structure that defines the positioning references for subsequent contact features. This preliminary action establishes a framework that guides the formation of non-self-aligned contacts, ensuring they are positioned at appropriate distances from the gate structure to minimize parasitic capacitance while maintaining manufacturability
Data Source
AI summary
A semiconductor structure includes a circuit cell having transistors. Each of the transistors includes nanostructures vertically stacked from each other, and a gate structure wrapped around the nanostructures and extending in a first direction. The semiconductor structure further includes a dielectric gate structure extending in the first direction and adjacent to the circuit cell in a second direction. The second direction is perpendicular to the first direction. The semiconductor structure further includes a first source/drain feature between adjacent two of the gate structures, a second source/drain feature between one of the gate structures and the dielectric gate structure, a first source/drain contact over the first source/drain feature and having a first width in the second direction, and a second source/drain contact over the second source/drain feature and having a second width in the second direction. The second width is greater than the first width.