Gate-All-Around Contact Structure for Lower Contact Resistance
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity and complexity in semiconductor manufacturing processes, which hinders the advancement of low-cost, high-performance, and low-power integrated circuits.
Innovation Solution
The method involves forming gate-all-around transistor structures with nanostructures surrounded by gate dielectric layers and source/drain structures, where contact structures are directly connected to reduce contact resistance, utilizing photolithography and self-aligned processes for patterning, and epitaxial growth for semiconductor material formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are integrated to improve gate control and reduce OFF-state current, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure completely surrounds the channel region in a nested configuration, with the gate electrode positioned within recesses formed in the semiconductor substrate. This nested gate-all-around structure provides enhanced gate control over the channel while maintaining a systematic manufacturing approach that addresses the complexity issue through structured process integration.
Solution Approach 2:
The invention transitions from planar gate structures to three-dimensional gate-all-around structures by forming gates that wrap around the channel region in multiple dimensions. This dimensional change enables superior gate control and electrostatic management while the patent provides detailed manufacturing methods to handle the increased structural complexity.
2Reliability
If conventional contact structures are used, then manufacturing is simpler, but contact resistance is higher
Solution Approach 1:
The contact structure is divided into multiple segments including contact holes formed through dielectric layers, contact pads positioned at specific locations, and interconnect structures that bridge different contact points. This segmentation allows for optimized electrical connections with reduced resistance while maintaining manufacturability through standardized fabrication processes.
Solution Approach 2:
Contact holes and contact pads are formed at predetermined locations and depths during the fabrication sequence, with doping regions prepared in advance to ensure low-resistance connections. This preliminary positioning and preparation of contact structures enables optimized electrical performance without adding excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor structures by reducing contact resistance and enhancing gate control, addressing the complexity in multi-gate device integration and advancing semiconductor manufacturing.
Implementation Method 1
utilizing photolithography and self-aligned processes for patterning
Implementation Method 2
epitaxial growth for semiconductor material formation
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.