Selective GAA Contact Capping for Uniform Low-Resistance Junctions
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Solution Overview
Problem
Existing methods for forming gate contact structures in gate-all-around field-effect transistors (GAA FETs) face challenges due to non-uniformity in silicide layer deposition, leading to variations in electrical characteristics and high resistance at MEOL contact junctions.
Innovation Solution
A method involving the removal of material from the surfaces of features in a semiconductor substrate, followed by selective formation of reaction product materials, metal layers, and filling with conductor materials like tungsten or molybdenum, to efficiently form reliable low resistance contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition techniques are used to form silicide layers in deep HAR holes/trenches, then the deposition process is simple and fast, but the species concentration gradient causes non-uniformity of deposition leading to variations in silicide layer properties and electrical characteristics
Solution Approach 1:
The deposition process is divided into multiple sequential steps: forming a first metal layer, selectively removing it from dielectric surfaces, forming a second metal layer, and selectively removing it. This segmentation allows each step to be optimized for uniformity while maintaining overall process manageability, directly addressing the non-uniform deposition problem in deep HAR structures
Solution Approach 2:
The method performs preliminary selective removal of the first metal layer from dielectric surfaces before forming the second metal layer. This preliminary action prevents non-uniformity from propagating through the entire silicide structure, ensuring that subsequent layers are formed on a uniformly prepared surface
2Length of moving object
If silicide contacts are formed on exposed portions of silicon-based source/drain layers in deep HAR holes, then contact structures are formed, but little to no space remains to reliably form GAA gate contact structures
Solution Approach 1:
The method applies different treatments to different locations: metal layers are selectively removed from dielectric surfaces while being retained on silicon-based contact structures. This local differentiation preserves contact structure reliability in deep HAR holes while creating sufficient space for gate contact structures elsewhere
Solution Approach 2:
The selective removal process operates in the vertical dimension within the HAR structures, differentiating between surfaces at different depths and orientations. This dimensional approach allows simultaneous optimization of contact structure reliability and gate contact space availability
3Reliability
If MEOL contact junctions have relatively high resistance, then connection quality deteriorates reducing overall device performance, but reducing resistance requires optimized deposition which increases process complexity
Solution Approach 1:
The method changes the physical and chemical parameters of the deposition process by using multiple metal layers with different properties and selective removal conditions. This parameter optimization achieves low resistance connections through controlled uniformity without requiring excessive process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves uniform and reliable formation of gate contact structures, reducing resistance and improving the overall performance of GAA FET devices by addressing non-uniformity issues in silicide layer deposition.
Implementation Method 1
heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts
Implementation Method 2
heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts
Implementation Method 3
selectively depositing the second metal layer on the first metal layer
Implementation Method 4
exposing the surface of the selectively formed first metal layer to a fluorine-free metal containing precursor to form the second metal layer
Implementation Method 5
Filling the feature with a conductor material, wherein the conductor material includes tungsten (W) or molybdenum (Mo)
Implementation Method 6
depositing a capping layer on the conductor material
Data Source
AI summary
Embodiments of the disclosure include a method of forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).