Deep GAA Source/Drain Contacts Reaching Multiple Channel Layers
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in reducing electrical resistance through the transistor and source/drain contacts, particularly due to the distance between channel layers and contacts being too far apart.
Innovation Solution
The formation of deep source/drain (S/D) contacts in GAA devices, which are designed to connect with all channel layers, reducing the distance and thereby lowering electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contacts are used in GAA devices, then the manufacturing process is simpler, but the electrical resistance through the transistor and contacts is too high
Solution Approach 1:
The patent transitions from conventional planar source/drain contacts to three-dimensional deep contacts that extend vertically through multiple channel layers. This dimensional change allows the contact to reach all channel layers directly, significantly reducing the resistance path length and improving electrical connectivity without requiring complex lateral interconnect structures.
Solution Approach 2:
The source/drain contact is segmented into multiple vertical portions, each extending through different channel layers. This segmentation allows the contact to be divided into discrete segments that can be independently optimized for each channel layer, improving overall electrical connectivity while maintaining manufacturability through standardized fabrication processes.
2Reliability
If deep source/drain contacts are formed to reduce resistance, then electrical resistance decreases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates preliminary actions during the fabrication process where contact etch stop layers and sacrificial structures are formed in advance to define the deep contact geometry. These preliminary structures guide subsequent etching processes to create the desired deep contacts with precise control over depth and lateral dimensions, making the complex 3D contact formation achievable through standardized process steps.
Solution Approach 2:
The patent uses intermediary structures such as contact etch stop layers and sacrificial gate dielectric materials that facilitate the formation of deep contacts. These intermediary layers serve as temporary or permanent barriers that enable precise control over contact depth and geometry, allowing complex 3D contact structures to be formed using conventional lithography and etching processes.
3Reliability
If source/drain contacts are positioned closer to channel layers, then electrical resistance decreases, but the contact structure becomes more complex
Solution Approach 1:
The patent implements a nested structure where the deep source/drain contact is positioned within the gate-all-around structure. The contact is nested such that it extends through multiple channel layers while remaining contained within the overall device footprint, allowing close proximity to all channel layers without increasing lateral device complexity.
Solution Approach 2:
Instead of increasing lateral contact size or complexity to reduce resistance, the patent solves the problem by extending contacts vertically into the third dimension. This allows the contact to be positioned close to all channel layers through direct vertical connectivity, eliminating the need for complex lateral interconnect structures while achieving low resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the electrical resistance in GAA devices, particularly beneficial for PMOS transistors in SRAM cells, without significantly impacting performance.
Implementation Method 1
etching the interlayer dielectric layer and the contact etch stop layer to expose a top portion of the source/drain feature
Implementation Method 2
forming a metallic contact in the contact trench... significantly reduce electrical resistance
Data Source
AI summary
A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.