GAA Source-Drain Contacts Across Variable CPP Canyons
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Solution Overview
Problem
Gate-All-Around (GAA) transistors face challenges in bottom dielectric isolation punch-through and contact landing on unmerged epi in wide PC-PC canyons, particularly in large gate-to-gate spaces, which affect power consumption, performance, and manufacturing costs.
Innovation Solution
The implementation of a method that simulates a constant canyon space design for any Contacted gate Poly Pitch (CPP) and gate length using simple spacers, allowing for reliable land trench metal contact on merged epi and improving Si surface availability for S/D epi nucleation, thereby preventing bottom dielectric isolation punch-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If finFET dimensions are reduced to scale transistors, then device area and cost are reduced, but drive current and electrostatic control deteriorate due to uncontrolled bottom sides and increased leakage
Solution Approach 1:
The patent transitions from planar finFET geometry to three-dimensional Gate-All-Around (GAA) nanosheet structures, where the gate wraps completely around the channel in all spatial dimensions. This dimensional change provides electrostatic control from all sides of the channel, eliminating the uncontrolled bottom surface issue in finFETs while maintaining scaled device footprints.
Solution Approach 2:
The gate structure completely surrounds and encloses the nanosheet channel, with the gate dielectric and gate electrode nested around the channel in a concentric configuration. This nested geometry ensures that the gate controls the channel from all directions (top, bottom, and sides), providing superior electrostatic control compared to partial-gate finFET structures.
2Length of moving object
If gate length is reduced to scale transistors, then device area is reduced, but short channel effects and leakage increase due to uncontrolled bottom of device
Solution Approach 1:
The patent implements Gate-All-Around geometry where the gate extends in the vertical dimension to wrap around the nanosheet channel, providing control from the bottom surface that was previously uncontrolled in planar devices. This vertical gating dimension suppresses short channel effects even at reduced gate lengths by eliminating the electric field leakage path at the channel bottom.
3Device complexity
If single-fin devices are used at sub 5 nm nodes, then device simplicity is maintained, but drive current is insufficient to meet performance goals
Solution Approach 1:
The patent divides the channel into multiple thin nanosheet segments stacked vertically, with each nanosheet contributing to the total drive current. This segmentation allows the device to achieve high drive current equivalent to multiple side-by-side fins while maintaining a compact vertical stack footprint and enabling complete gate wrap-around for superior control.
Solution Approach 2:
Instead of increasing drive current by adding more fins in the lateral plane (increasing device footprint), the patent stacks multiple nanosheets in the vertical dimension. This vertical stacking provides increased current-carrying capacity while maintaining small device area and enabling Gate-All-Around control geometry.
4Reliability
If GAA transistors are implemented with wrapped gate material, then channel control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms the gate dielectric and gate electrode structures around the nanosheet channels before final channel definition, using preliminary sacrificial layers and spacer formation to pre-establish the Gate-All-Around geometry. This preliminary structuring simplifies subsequent processing steps and enables complex three-dimensional gate wrapping through systematic sequential fabrication rather than attempting to form the entire structure in one step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of transistors with improved power efficiency, performance, reduced area occupation, and lower manufacturing costs by ensuring reliable contact formation and nucleation in GAA devices.
Implementation Method 1
source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation (BDI) region
Implementation Method 2
improves the Si surface available for S/D epi nucleation
Data Source
AI summary
A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.