GAA Nanostructure Corner Rounding for Gate Dielectric Coverage
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes as feature sizes continue to decrease, making it difficult to achieve consistent and efficient manufacturing.
Innovation Solution
A semiconductor device structure is formed using a gate-all-around (GAA) transistor design, where nanostructures are patterned through photolithography and self-aligned processes, followed by an oxidation process to round corners, improving the coverage and reliability of gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and reliability increase
Solution Approach 1:
The patent applies preliminary action by performing corner rounding on the fin structure before forming the gate dielectric layer. This pre-treatment ensures that the gate dielectric can be deposited with uniform thickness and complete coverage from the outset, preventing reliability issues that would otherwise arise at scaled dimensions. The corner rounding is done in advance to eliminate potential defects before they can affect device performance.
Solution Approach 2:
The patent implements spheroidality by rounding the corners of the fin structure to create curved surfaces instead of sharp angles. This curvature eliminates stress concentration points and enables uniform gate dielectric coverage, directly addressing the reliability challenges associated with continued scaling while maintaining the benefits of high functional density.
2Manufacturing precision
If feature sizes continue to decrease, then functional density increases, but fabrication process complexity increases
Solution Approach 1:
The patent reduces fabrication complexity by performing corner rounding as a preliminary step before gate dielectric formation. This pre-treatment simplifies subsequent processing by ensuring uniform surfaces that are easier to coat, thereby reducing the overall complexity of the fabrication process while maintaining the required manufacturing precision for scaled features.
Solution Approach 2:
The patent applies parameter changes by modifying the geometry of the fin structure through corner rounding. This geometric parameter change creates more favorable conditions for subsequent processing steps, such as gate dielectric deposition, thereby reducing fabrication complexity while maintaining the precision required for small feature sizes.
3Reliability
If corner rounding is performed to improve gate dielectric coverage, then device reliability improves, but additional processing steps are required
Solution Approach 1:
The patent merges the corner rounding step with the existing fin formation process. By integrating the rounding operation into the sequence of steps already required to create the fin structure, the patent achieves improved gate dielectric coverage and device reliability without adding significant process complexity. The rounding is performed as part of the natural workflow rather than as a separate, standalone operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The rounding of corners enhances the yield and reliability of the semiconductor device by improving the coverage of gate dielectric layers, addressing the challenges of forming reliable devices at smaller scales.
Implementation Method 1
an oxidation process to round corners
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, and a first gate stack. The first nanostructure is between the substrate and the second nanostructure, and the first gate stack is wrapped around the first nanostructure and the second nanostructure. The method includes removing the first gate stack and end potions of the first nanostructure. The method includes partially removing the second nanostructure to round a first corner of the second nanostructure. The first corner becomes a first rounded corner after the second nanostructure is partially removed. The method includes removing the first nanostructure. The method includes forming a second gate stack over the substrate and wrapped around the second nanostructure.