Gate-All-Around Cut Gate Spacers to Prevent Shorts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits faces challenges in maintaining mobility and short channel control as dimensions approach the 10 nanometer node, with constraints on lithographic processes leading to trade-offs between feature dimension and spacing, resulting in issues like gate end-to-end shorts and contact side-to-side shorts.
Innovation Solution
The implementation of a pre-spacer-deposition cut gate approach with a spacer etch-back process, allowing for independent tuning of spacer thickness to fill poly cut spaces and gate sidewall spacers, decoupling the thickness of the spacer in the poly cut from the gate sidewall, and using dissimilar spacer materials with isotropic etch selectivity to minimize exposed surfaces and prevent etch loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and process complexity is simplified, but gate end-to-end shorts and contact side-to-side shorts occur due to lithographic constraints
Solution Approach 1:
The fabrication process is divided into separate stages: first forming the gate structure, then performing spacer deposition, and finally executing the poly cut after spacer formation. This segmentation allows each step to be optimized independently, eliminating the shorts issue while maintaining manufacturing efficiency
Solution Approach 2:
Spacers are deposited and formed before the poly cut is executed. This preliminary action creates a protective structure that prevents gate end-to-end shorts and contact side-to-side shorts during subsequent processing steps
2Reliability
If spacer thickness is increased to fill poly cut spaces, then gate end-to-end shorts are prevented, but gate height loss increases
Solution Approach 1:
The spacer structure is designed with different thicknesses in different locations: thicker spacers in the poly cut regions to prevent shorts, and thinner spacers on the gate sidewalls to minimize height loss. This local differentiation optimizes both reliability and dimensional control
3Manufacturing precision
If dissimilar spacer materials with isotropic etch selectivity are used, then etch loss is minimized and exposed surfaces are reduced, but material selection and process complexity increase
Solution Approach 1:
A composite spacer structure is formed using dissimilar materials (e.g., silicon nitride and silicon oxide) with specific isotropic etch selectivity ratios. This composite approach minimizes etch loss and reduces exposed surfaces while the selectivity ratio is optimized to balance material complexity with manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process flow, reduces gate height loss, and effectively eliminates the marginality between gate end-to-end and contact side-to-side shorts, enabling very small critical dimensions and high transistor density while maintaining desirable fin stress for improved carrier mobility.
Implementation Method 1
a spacer material is formed over the starting structure
Implementation Method 2
subsequent spacer material etching can be implemented to leave the portion 218A remaining only along the sidewalls of the gate lines 212, while retaining the second portion 218B in the narrow poly cut 216
Data Source
AI summary
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.