Deep Source/Drain Contacts in GAA Devices for Lower Resistance
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in reducing electrical resistance through the transistor and source/drain contacts, particularly due to the distance between channel layers and contacts, which is exacerbated in PMOS transistors like pull-up transistors of SRAM cells.
Innovation Solution
The formation of deep source/drain (S/D) contacts that reduce the distance between channel layers and contacts by epitaxially growing S/D features from exposed surfaces of semiconductor layers, thereby reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contacts are used in GAA devices, then manufacturing is simpler, but electrical resistance through the transistor and contacts is high
Solution Approach 1:
The patent transitions from conventional shallow source/drain contacts to deep source/drain contacts that extend vertically through multiple channel layers. This dimensional change in contact depth enables better electrical connection to all channel layers while maintaining compatibility with existing GAA device architecture and manufacturing processes.
Solution Approach 2:
The source/drain contact structure is segmented into multiple portions, with each portion extending through different channel layers. This segmentation allows the contact to selectively connect to specific channel layers while maintaining overall electrical integrity and reducing resistance through the entire transistor structure.
2Reliability
If deep source/drain contacts are formed to reduce resistance, then electrical resistance decreases, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary actions by forming mandrels and sacrificial structures before creating the final deep source/drain contacts. These preliminary structures guide the subsequent etching and filling processes, making the formation of deep contacts more controllable and less complex than direct formation would suggest.
Solution Approach 2:
The patent uses intermediary materials and structures (such as mandrels, sacrificial gate dielectric layers, and etch stop layers) to facilitate the creation of deep source/drain contacts. These intermediaries enable precise control over contact depth and positioning while simplifying the overall manufacturing process by breaking down complex steps into manageable stages.
3Reliability
If source/drain contacts are positioned closer to channel layers to reduce distance, then electrical resistance decreases, but device structure becomes more complex
Solution Approach 1:
The patent employs self-aligned formation methods where the source/drain contacts are automatically positioned relative to the channel layers through the use of self-aligned mandrels and sacrificial structures. This self-service approach eliminates the need for complex alignment procedures while ensuring optimal contact positioning to minimize resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The deep S/D contacts effectively lower electrical resistance in GAA devices, particularly benefiting PMOS transistors by maintaining performance while minimizing strain impacts.
Implementation Method 1
The formation of deep source/drain (S/D) contacts that reduce the distance between channel layers and contacts by epitaxially growing S/D features from exposed surfaces of semiconductor layers
Data Source
AI summary
A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.