Gate-All-Around Deep Via Contacts for Sub-Fin Charge Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication is the lack of a reliable electrical contact between nanowire or nanoribbon transistors and the underlying silicon substrate, which hinders effective charge dissipation during in-process charging and electrostatic discharge events, leading to potential circuit malfunction.
Innovation Solution
The introduction of a deep via substrate contact that connects nanowires or nanoribbons to the silicon substrate, allowing for charge dissipation and ensuring circuit functionality, involves patterning and etching operations to create a conductive contact on the substrate, which can be filled with a conductive material and optionally doped or epitaxially grown, and can coincide with or be separate from the source/drain/gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanowire or nanoribbon transistors are fabricated without deep via substrate contacts, then device density and scaling are improved, but electrical contact and charge dissipation capability deteriorate
Solution Approach 1:
The substrate contact is segmented into multiple deep via contacts distributed across the device structure. Each deep via provides an independent electrical contact path from the nanowire/nanoribbon channel to the substrate, ensuring reliable charge dissipation while maintaining high device density through optimized spatial distribution.
Solution Approach 2:
The contact structure transitions from a planar surface contact to a vertical deep via structure penetrating through the device stack. This dimensional change enables electrical contact through the third dimension (depth), allowing charge dissipation paths that do not interfere with the planar device footprint and thus maintaining high device density.
2Reliability
If deep via substrate contacts are added to nanowire transistors, then charge dissipation and circuit reliability are improved, but manufacturing complexity increases
Solution Approach 1:
The deep via formation process is merged with existing fabrication steps such as source/drain contact formation or gate patterning. By combining multiple functions into a single process sequence, the manufacturing complexity is reduced while still achieving the necessary deep via substrate contacts for reliable circuit operation.
Solution Approach 2:
The deep via structure serves multiple functions: providing electrical contact to the substrate, enabling charge dissipation during IPC and ESD events, and potentially serving as a mechanical support structure. This multi-functionality reduces the need for additional specialized structures, thereby simplifying the overall fabrication process.
3Ease of manufacture
If the deep via contact coincides with source/drain/gate structures, then manufacturing steps are reduced, but electrical isolation and device performance may be compromised
Solution Approach 1:
The deep via contact structure is designed with locally optimized properties: the via walls are lined with specific barrier and seed layers tailored to the local electrical isolation requirements, while the via fill material is selected to provide appropriate conductivity. This local quality control ensures that even when the deep via coincides with source/drain/gate structures, electrical isolation is maintained through precise material selection and layer design at each location.
Data Source
AI summary
Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.