GAA Transistor Defect Detection Using Multi-Energy SEM Imaging
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Solution Overview
Problem
Existing defect detection methods for gate-all-around (GAA) transistors, particularly in epitaxial fill regions, fail to distinguish between top and buried defects, leading to inefficiencies in yield loss identification and delayed detection.
Innovation Solution
A method combining optical inspection with high-resolution scanning electron microscopy (SEM) using multiple landing energies to generate images, analyzing contrast-to-noise ratios (CNR) at different depths to classify defects as top, buried, or completely missing epitaxial fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing defect detection methods are used, then defect detection is performed, but top and buried defects cannot be distinguished
Solution Approach 1:
The defect detection process is segmented into multiple inspection steps using different landing energies. Low landing energy (1-5 kV) inspects top defects near the surface, while high landing energy (5-30 kV) inspects buried defects deeper in the epitaxial fill region. This segmentation allows distinct detection of defects at different depths without interference.
Solution Approach 2:
The landing energy parameter of the electron beam is changed between inspection steps to achieve different detection depths. By adjusting the landing energy from low (1-5 kV) to high (5-30 kV), the inspection system can selectively detect defects at different depths within the epitaxial fill region, enabling classification of top versus buried defects.
2Measurement precision
If high-resolution SEM is used, then defect detection capability is improved, but inspection time and complexity increase
Solution Approach 1:
Optical inspection is performed as a preliminary step before SEM inspection to identify locations of potential defects. This preliminary action filters the inspection area, so that high-resolution SEM is only applied to regions where defects are suspected, significantly reducing the total inspection time while maintaining high detection capability.
Solution Approach 2:
Instead of performing full high-resolution SEM inspection across the entire wafer, the method applies SEM only partially to regions identified by optical inspection as containing potential defects. This partial action approach maintains high detection resolution where needed while avoiding unnecessary inspection time in defect-free regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables immediate detection and classification of defects during semiconductor fabrication, reducing yield loss and improving production efficiency by distinguishing between yield-killing top defects and tolerable buried defects.
Implementation Method 1
a first scanning electron microscope (SEM) image of the location of the defect is obtained using a first landing energy that is tuned to detect top defects; a second SEM image of the location of the defect is obtained using a second landing energy that is tuned to detect buried defects
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods to detect defects in gate-all-around transistor architectures are disclosed. An apparatus includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine a first contrast to noise ratio (CNR) in a first image of a location on a semiconductor wafer; determine a second CNR in a second image of the location on the semiconductor wafer; and determine whether the location includes a buried defect based on the first CNR and the second CNR.