GAA Source/Drain Dielectric Structure for Bridging and Capacitance
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Solution Overview
Problem
As semiconductor devices scale down, there is a challenge in improving processing and manufacturing efficiency while maintaining device density and performance, particularly in preventing gate-to-source/drain bridging and reducing device capacitance in gate-all-around transistors.
Innovation Solution
The solution involves forming a stack of semiconductor layers with alternating first and second semiconductor layers, where the second semiconductor layers are replaced with a dielectric material of different etch selectivity in the source/drain regions, and a high-k dielectric layer is replaced with a lower-k dielectric material to reduce capacitance and prevent bridging, using a combination of photolithography and self-aligned processes for patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then functional density increases, but gate-to-source/drain bridging occurs and manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The source/drain regions are segmented into first source/drain regions and second source/drain regions with different dielectric materials. This segmentation allows different etch selectivities in different regions, preventing gate-to-source/drain bridging while maintaining small device dimensions and high device density.
Solution Approach 2:
Different dielectric materials are used in different local regions (first source/drain regions vs. second source/drain regions). The first dielectric material has different etch selectivity than the second dielectric material, allowing localized control of etching processes to prevent bridging in critical areas while maintaining overall device density.
2Reliability
If high-k dielectric layer is used to improve gate control, then device performance improves, but device capacitance increases
Solution Approach 1:
The dielectric structure is made non-uniform by using different dielectric materials in different regions. The first dielectric material and second dielectric material have different properties, allowing optimization of gate control in some regions while reducing capacitance in other regions, thus resolving the contradiction between gate control and capacitance.
Solution Approach 2:
The device uses a composite dielectric structure combining first dielectric material and second dielectric material. This composite structure allows the device to benefit from high-k dielectric properties for gate control while using lower-k second dielectric material in source/drain regions to reduce overall device capacitance.
3Manufacturing precision
If photolithography and self-aligned processes are used for patterning, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The first dielectric layer and second dielectric layer are formed in a predetermined stacked configuration before final patterning. This preliminary arrangement of materials with different etch selectivities enables subsequent self-aligned processes to automatically achieve precise patterning without requiring additional complex alignment steps, thus improving manufacturing precision while limiting complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved device density, reduced capacitance, and enhanced scalability with reduced gate-to-source/drain bridging, leading to more efficient and effective semiconductor device manufacturing.
Implementation Method 1
a high-k dielectric layer is replaced with a lower-k dielectric material to reduce capacitance
Implementation Method 2
the second semiconductor layers are replaced with a dielectric material of different etch selectivity in the source/drain regions
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.