GAA Dielectric Lateral Etching for Metal Gate CD Control
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Solution Overview
Problem
Existing methods face challenges in configuring the critical dimension of metal gate structures in gate-all-around (GAA) devices, particularly due to issues with etching processes that result in undesirable profiles of dummy oxide layers, affecting device performance as device sizes are scaled down.
Innovation Solution
A method involving the formation of a stack of semiconductor layers with alternating compositions, followed by selective etching of dielectric layers at controlled pressures and temperatures, and subsequent replacement of dummy gate stacks with metal gates, ensuring precise control over the lateral dimensions of the metal gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove dummy oxide layers, then the etching process is simple and fast, but the lateral dimension configuration of metal gate structures becomes difficult and device performance degrades
Solution Approach 1:
The patent applies parameter changes by modifying etching process conditions (temperature, pressure, gas composition) to achieve precise control over dummy oxide layer removal. Specifically, the etching process is conducted at temperatures between 16°C and 20°C and pressures between 600-800 milli-Torrs, which enables accurate lateral dimension configuration of metal gate structures while maintaining reasonable process complexity
Solution Approach 2:
The patent implements dynamics by making the etching process adjustable and controllable through dynamic parameter modification. The process can be tuned by varying temperature, pressure, and gas flow rates to achieve desired etching profiles, transforming a static simple etching process into a dynamic controllable process that balances precision and complexity
2Productivity
If device sizes are scaled down to improve production efficiency and lower costs, then productivity increases, but configuring lateral dimensions of metal gate structures becomes more difficult
Solution Approach 1:
The patent uses parameter changes to maintain manufacturing precision during device scaling. By controlling etching temperature (16°C-20°C) and pressure (600-800 milli-Torrs), the process achieves accurate lateral dimension configuration even as device sizes decrease, enabling continued productivity improvement without sacrificing precision
3Length of moving object
If aggressive scaling down of IC technologies is pursued to meet demand for smaller devices, then device size reduces and production efficiency improves, but gate structure configuration becomes increasingly difficult
Solution Approach 1:
The patent applies parameter changes to facilitate gate structure configuration during aggressive scaling. The controlled etching parameters (temperature 16°C-20°C, pressure 600-800 milli-Torrs) enable precise gate structure formation at smaller device dimensions, maintaining ease of manufacture despite scaling challenges
Solution Approach 2:
The patent replaces conventional mechanical/physical etching approaches with a chemically-controlled etching process using specific gas compositions and controlled environmental parameters. This substitution enables more precise gate structure configuration at scaled dimensions compared to traditional mechanical etching methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of GAA devices with improved metal gate profiles, reducing doping diffusion, built-in stress, and enhancing silicon performance while mitigating short-channel effects and decreasing capacitance between source/drain regions.
Implementation Method 1
an etching process is performed to the dielectric layers at a process temperature between about 16 degrees Celsius and about 20 degrees Celsius and at a process pressure between about 600 milli-Torrs and about 800 milli-Torrs
Data Source
AI summary
A stack of first semiconductor layers and second semiconductor layers is formed. The first semiconductor layers each have a first material composition. The second semiconductor layers each have a second material composition different from the first material composition. The first semiconductor layers interleave with the second semiconductor layers in the stack. The second semiconductor layers are replaced with a plurality of dielectric layers. An etching process is performed to the dielectric layers. The etching is performed at a process pressure between about 600 milli-Torrs and about 800 milli-Torrs or at a process temperature between about 16 degrees Celsius and about 20 degrees Celsius.