GAA Source/Drain Patterning With Multilayer Dielectric Masks
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor devices in semiconductor manufacturing is challenging due to the complexity of fabricating features around nanowires, necessitating improved methods for patterning and forming source/drain regions.
Innovation Solution
A method involving the use of a silicon-containing dielectric mask layer and a high-k dielectric mask layer to pattern source/drain features, allowing for the formation of GAA structures with enhanced process window and reduced loss of low-k spacers, utilizing epitaxial growth and self-aligned processes to create fin structures and isolation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional methods are used to fabricate GAA features around nanowires, then the basic device structure can be formed, but the process complexity increases and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the patterning process into multiple stages using a multi-layer mask structure. The first mask layer patterns source/drain regions, the second mask layer patterns channel regions, and the third mask layer performs final patterning. This segmentation allows each layer to be optimized for specific patterning requirements, reducing overall process complexity while maintaining high precision.
Solution Approach 2:
The patent introduces a vertical multi-layer mask structure to solve planar patterning limitations. By stacking mask layers at different heights (first mask layer at bottom, second mask layer in middle, third mask layer at top), the process achieves complex 3D feature definition while maintaining precision that would be difficult to obtain with single-layer planar masks.
2Productivity
If feature size is scaled down to improve production efficiency and lower costs, then productivity increases, but manufacturing precision and process complexity worsen
Solution Approach 1:
The patent performs preliminary patterning actions using the first and second mask layers before final patterning. The first mask layer pre-defines source/drain regions, and the second mask layer pre-defines channel regions. This preliminary action reduces the burden on the final patterning step, allowing smaller features to be formed with higher precision while maintaining productivity.
Solution Approach 2:
The multi-layer mask structure acts as an intermediary between the photolithography process and the final nanoscale features. The mask layers translate larger photolithography patterns into precise nanoscale features through selective etching and material removal, enabling scaling to smaller dimensions while maintaining manufacturing precision.
3Manufacturing precision
If multi-layer mask structure is used to improve patterning precision, then manufacturing precision improves, but device complexity and process steps increase
Solution Approach 1:
Each mask layer in the multi-layer structure serves multiple functions. The first mask layer not only patterns source/drain regions but also serves as a foundation for subsequent mask layers. The second mask layer patterns channel regions while providing structural support. This multi-functionality reduces the need for additional dedicated layers, balancing precision improvement with process complexity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise patterning of GAA transistors with improved gate control and reduced short-channel effects, enhancing the performance and efficiency of semiconductor devices.
Implementation Method 1
forming a silicon-containing dielectric mask layer and a high-k dielectric mask layer over the silicon-containing dielectric mask layer
Implementation Method 2
patterning the dielectric mask layers into a source/drain mask structure that covers a device region and exposes another device region
Implementation Method 3
utilizing epitaxial growth and self-aligned processes to create fin structures and isolation layers
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region, etching the first active region and the second active region to form a first recess and a second recess, respectively, forming the first dielectric layer over the first active region and the second active region, forming a first fill layer over the first dielectric layer to overfill the first recess and the second recess, forming a first dielectric mask over the first fill layer, etching first portions of the first dielectric mask and the first fill layer over the first active region, removing a first portion of the first dielectric layer over the first active region, and forming a first source/drain feature on the first active region.