GAA Semiconductor Structure With Dielectric Wall Isolation

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Solution Overview

Problem

The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity and the need for advanced processes to improve gate control, reduce OFF-state current, and mitigate short-channel effects.

Innovation Solution

The implementation of a gate all around (GAA) transistor structure with a dielectric wall structure that isolates adjacent source/drain structures and separates the gate structures, preventing unwanted connections and reducing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-gate devices are integrated to improve gate control and reduce OFF-state current, then device performance is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvegate controlVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is segmented into multiple gates surrounding the channel (multi-gate structure), with each gate independently controlling a portion of the channel. This segmentation enables improved gate control and reduced OFF-state current while maintaining manufacturability through modular fabrication processes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The multi-gate structure implements a nested configuration where gates are positioned around the channel in a nested arrangement, allowing successive gates to control progressively deeper portions of the channel. This nested architecture improves control effectiveness while enabling systematic integration in the manufacturing process

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If device dimensions are scaled down to improve production efficiency and lower costs, then productivity is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidmanufacturing process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention transitions from planar 2D device structures to three-dimensional multi-gate configurations. By adding the vertical dimension and surrounding gates around the channel, the device achieves improved control and scalability without requiring proportional increases in manufacturing process complexity, as the same fabrication techniques can be applied in multiple dimensions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250133788A1Semiconductor structure and method for forming the same
Publication Date: 2025.04.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250133788A1 patent drawing
  • US20250133788A1 patent drawing
  • US20250133788A1 patent drawing

AI summary

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a first S/D structure formed adjacent to the first gate structure. The semiconductor structure includes a second gate structure formed over the second nanostructures along the second direction, and a second S/D structure formed adjacent to the second gate structure. The semiconductor structure includes a dielectric wall structure formed along the first direction. The dielectric wall structure includes a first portion between the first S/D structure and the second S/D structure and a second portion between the first gate structure and the second gate structure.