GAA Semiconductor Structure With Dielectric Wall Separation Control
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and narrower separation distances, which poses challenges in maintaining reliability and integration due to the reduction in size of planar metal oxide semiconductor FETs.
Innovation Solution
A semiconductor device design featuring a dielectric wall structure with specific width variations and gate structures that include multiple channel layers and source/drain regions, along with a gate-all-around type field effect transistor configuration, enhances integration and reliability by stabilizing gate and source/drain separations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of planar metal oxide semiconductor FET is reduced to achieve finer patterns, then the degree of integration is improved, but the operating properties and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional vertical channel structure by forming channel layers stacked in the vertical direction. This dimensional change allows the device to achieve higher integration density while maintaining reliable electrical properties through the vertical gate-all-around configuration that provides effective channel control without further lateral scaling.
Solution Approach 2:
The gate structure completely surrounds the channel layers in a nested configuration, with the gate electrode wrapping around the vertical channel structure from all sides. This nested gate-all-around design provides enhanced electrostatic control over the channel while maintaining compact device footprint, resolving the contradiction between integration density and operational reliability.
2Quantity of substance
If the separation distance between gate and source/drain is reduced to achieve finer patterns, then the degree of integration is improved, but the manufacturing precision and reliability worsen due to instability
Solution Approach 1:
The patent employs selective width variations in the dielectric wall structure, where the lower dielectric wall has a first width and the upper dielectric wall has a second width less than the first width. This local quality change creates stable separation distances in critical regions while allowing integration density to increase in other areas, preventing manufacturing variability.
3Ease of manufacture
If the dielectric wall structure uses uniform width throughout, then the manufacturing process is simpler, but the separation stability between gate and source/drain deteriorates
Solution Approach 1:
The dielectric wall structure implements different widths at different vertical levels, with the lower portion having a larger width for stability and the upper portion having a smaller width for integration density. This local differentiation maintains manufacturing feasibility while achieving stable separation characteristics in the critical gate-source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the degree of integration and reliability of semiconductor devices by maintaining stable separation of gate electrodes and source/drain regions, preventing losses during manufacturing processes.
Implementation Method 1
a first upper dielectric wall on the lower dielectric wall, the first upper dielectric wall including a material having a dielectric constant, lower than that of the lower dielectric wall
Data Source
AI summary
A semiconductor device includes a substrate, a dielectric wall structure extending in a first direction on the substrate, active regions extending in the first direction, a gate structure extending in a second direction on the substrate, intersecting the dielectric wall structure, a plurality of channel layers on the active regions and spaced apart from each other in a third direction surrounded by the gate structure, and source/drain regions on at least one side of the gate structure. The dielectric wall structure includes a lower dielectric wall extending in the first direction, and a first upper dielectric wall overlapping the gate structure in the second direction, on the lower dielectric wall. A first upper surface of the lower dielectric wall in contact with the first upper dielectric wall has a first width, and a lower surface of the first upper dielectric wall has a second width less than the first width.