GAA Fin Structure With Dummy Wall Fin for Epitaxial Separation
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Solution Overview
Problem
In the semiconductor industry, particularly for gate-all-around (GAA) FETs, the challenge lies in achieving optimal source/drain epitaxial structure shapes to enhance Ion/Ioff current ratios and device performance, as existing methods often result in undesired merging of epitaxial layers between adjacent fin structures.
Innovation Solution
The implementation of a wall fin structure using a dielectric dummy fin to physically and electrically separate adjacent source/drain epitaxial layers, defined by a specific manufacturing process involving alternating semiconductor layers, etching, and the formation of various dielectric and sacrificial layers to control the shape and separation of these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for source/drain epitaxial structures, then device density and manufacturing simplicity are maintained, but undesired merging of epitaxial layers between adjacent fin structures occurs, reducing device performance
Solution Approach 1:
The patent introduces a dummy fin structure that physically segments and separates adjacent fin structures, preventing the merging of source/drain epitaxial layers. This segmentation approach creates distinct isolation regions between fins, ensuring precise spatial separation of epitaxial growth zones while maintaining manufacturability through standard lithography and etching processes
Solution Approach 2:
The dummy fin acts as an intermediary structure between adjacent real fins, providing a physical barrier that prevents direct interaction and merging of epitaxial layers. This mediator structure enables precise control over epitaxial layer separation without requiring complex processing steps, as the dummy fin can be formed using conventional fabrication techniques
2Reliability
If gate-all-around structure is implemented to improve channel control, then short-channel effects are reduced, but manufacturing complexity increases due to the need for precise epitaxial layer shaping
Solution Approach 1:
The patent employs preliminary action by forming the dummy fin structure and defining the separation regions before the source/drain epitaxial growth process. This pre-established geometric framework guides the subsequent epitaxial deposition, ensuring that layers grow in the desired separated configuration without requiring complex in-situ control during the growth process itself
Solution Approach 2:
The dummy fin structure creates local quality differences in the fabrication environment, establishing distinct regions with different growth conditions. Areas near the dummy fin experience suppressed epitaxial growth while regions away from it allow normal growth, enabling precise spatial control of layer formation to maintain channel integrity for GAA FET operation
3Ease of manufacture
If epitaxial layers are allowed to merge between adjacent fins, then manufacturing simplicity is maintained, but Ion/Ioff current ratio deteriorates due to loss of electrical separation
Solution Approach 1:
The dummy fin structure segments the fabrication field into distinct zones, preventing the merging of source/drain epitaxial layers between adjacent fins. This segmentation maintains electrical isolation necessary for achieving good Ion/Ioff current ratios while using simple, scalable fabrication processes that can be integrated into existing manufacturing lines
Solution Approach 2:
The dummy fin serves as an intermediary barrier that physically prevents epitaxial layer merging while allowing the rest of the manufacturing process to remain simple and conventional. This mediator enables electrical separation for improved current ratio without introducing complex processing steps, as the dummy fin can be removed or integrated in subsequent standard fabrication stages
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.