GAA Gate Spacers and End Dielectric for Short-Circuit Isolation
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Solution Overview
Problem
The challenge in fabricating gate-all-around (GAA) devices is the occurrence of short circuits between source/drain contacts and gates, insufficient gate isolation, and increased stray capacitance due to metal diffusion and scaling limitations, which affect the reliability and performance of integrated circuits.
Innovation Solution
The introduction of new gate spacer designs combined with dielectric fins for self-aligned contact schemes and a highly reliable gate-end dielectric scheme between gate ends, along with multiple spacer schemes for gate sidewalls, to reduce stray capacitance and enhance gate isolation, thereby improving device density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate-all-around devices are scaled down to improve integration density, then device density increases, but short circuits between source/drain contacts and gates occur due to insufficient gate isolation
Solution Approach 1:
The gate structure is segmented into multiple components including gate spacers, gate end dielectric features, and gate top dielectric layers. These segmented elements work together to provide comprehensive gate isolation, preventing short circuits while enabling continued device scaling and improved integration density.
Solution Approach 2:
Gate end dielectric features are introduced as intermediary elements between the gate structure and source/drain contacts. These dielectric features act as mediators that enhance gate isolation and prevent direct electrical contact between gates and source/drain regions, thereby eliminating short circuit issues.
2Ease of manufacture
If conventional gate structures are used in scaled devices, then manufacturing simplicity is maintained, but stray capacitance increases due to metal diffusion and scaling limitations
Solution Approach 1:
The gate structure extends into the vertical dimension with gate spacers on sidewalls and gate end dielectric features at terminations. This three-dimensional configuration increases the effective isolation volume without significantly increasing lateral footprint, thereby reducing stray capacitance while maintaining manufacturing compatibility.
Solution Approach 2:
The gate structure employs composite dielectric materials with different properties in different regions: gate spacers provide sidewall isolation, gate end dielectric features provide termination isolation, and gate top dielectric provides planarization. This composite approach optimizes stray capacitance reduction while maintaining ease of manufacture through established deposition techniques.
3Reliability
If gate isolation is enhanced to prevent short circuits, then reliability improves, but device complexity increases due to additional spacer and dielectric structures
Solution Approach 1:
The gate spacers and gate end dielectric features serve multiple functions simultaneously: they provide gate isolation to prevent short circuits, define source/drain contact alignment, and enable self-aligned contact schemes. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Solution Approach 2:
Gate spacers and gate end dielectric features are formed in advance during the gate formation process, before source/drain contact fabrication. This preliminary action establishes the isolation structure and alignment references early in the process, simplifying subsequent contact formation and reducing overall process complexity.
Data Source
AI summary
A method includes providing a substrate, an isolation structure, a semiconductor fin having a stack of first and second semiconductor layers, a dummy gate, and outer spacers on opposing sidewalls of the dummy gate; etching the semiconductor fin to form source/drain (S/D) trenches; etching the second semiconductor layers from the S/D trenches to form gaps vertically between the first semiconductor layers; forming inner spacers in the gaps; epitaxially growing S/D features in the S/D trenches; forming an inter-layer dielectric layer over the S/D features; etching the dummy gate and the outer spacers to form a gate-end trench away from the semiconductor fin and over the isolation structure; and forming a gate-end dielectric feature filling the gate-end trench, wherein a dielectric constant of the gate-end dielectric feature is higher than both a dielectric constant of the outer spacers and a dielectric constant of the inner spacers.