GAA Source/Drain Epitaxy With Adhesion Layer for Leakage Control
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Solution Overview
Problem
Existing GAA transistor fabrication faces challenges due to source/drain layer discontinuity, leading to issues like high sub-threshold leakage, junction leakage, increased parasitic capacitance, and degraded SRAM yield, particularly in advanced semiconductor devices.
Innovation Solution
Incorporating an adhesion layer, such as di-borane or di-phosphorous based materials, to facilitate continuous growth of source/drain epitaxial layers, ensuring uniform coverage on both Si channel and SiN inner spacer surfaces, thereby overcoming the epitaxial merge issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA transistor fabrication is used, then manufacturing process simplicity is maintained, but source/drain layer discontinuity occurs leading to high sub-threshold leakage and degraded device performance
Solution Approach 1:
The method performs preliminary actions by forming adhesion layers on sidewall surfaces before epitaxial growth, and by selectively removing portions of source/drain layers to create trenches. These preliminary steps ensure continuous epitaxial layer formation and prevent source/drain discontinuity, thereby reducing sub-threshold leakage without requiring fundamentally new fabrication approaches
Solution Approach 2:
Adhesion layers serve as intermediary elements between the substrate and epitaxial source/drain layers. These adhesion layers facilitate continuous epitaxial growth by providing a stable interface that promotes uniform material deposition, preventing discontinuity and improving device reliability
2Manufacturing precision
If source/drain layers are formed without adhesion layers, then manufacturing steps are reduced, but epitaxial merge issue occurs causing layer discontinuity and increased parasitic capacitance
Solution Approach 1:
The method performs preliminary actions by forming adhesion layers on sidewall surfaces before epitaxial growth, and by selectively removing portions of source/drain layers to create trenches. These preliminary steps ensure continuous epitaxial layer formation and prevent source/drain discontinuity, thereby reducing sub-threshold leakage without requiring fundamentally new fabrication approaches
Solution Approach 2:
Adhesion layers serve as intermediary elements between the substrate and epitaxial source/drain layers. These adhesion layers facilitate continuous epitaxial growth by providing a stable interface that promotes uniform material deposition, preventing discontinuity and improving device reliability
3Length of moving object
If advanced scaling is implemented to improve device performance, then gate control is enhanced, but short-channel effects and leakage increase
Solution Approach 1:
The method segments the source/drain region by creating trenches through selective removal of source/drain layers. This segmentation allows for controlled epitaxial growth in isolated regions, improving gate control and reducing short-channel effects by creating distinct electrical regions that can be independently optimized
Solution Approach 2:
The method changes physical and chemical parameters by forming adhesion layers that modify surface properties, and by controlling epitaxial growth conditions to achieve continuous layer formation. These parameter changes enable better interface quality and reduced leakage in scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves GAA transistor performance by enhancing short-channel control, reducing sub-threshold leakage, and increasing SRAM cell yield and operational margin.
Implementation Method 1
Incorporating an adhesion layer, such as di-borane or di-phosphorous based materials, to facilitate continuous growth of source/drain epitaxial layers, ensuring uniform coverage on both Si channel and SiN inner spacer surfaces
Implementation Method 2
facilitate continuous growth of source/drain epitaxial layers, ensuring uniform coverage on both Si channel and SiN inner spacer surfaces
Data Source
AI summary
A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.