Nanowire Stack GAA Epitaxy with Faceted Trench Bottom Control
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Solution Overview
Problem
The challenge of short-channel effects in CMOS transistors, particularly in FinFETs, is addressed by developing gate-all-around (GAA) devices using separately formed nanowire semiconductor strips, where the growth of epitaxy layers is influenced by the shape of the trench bottom and sidewalls, necessitating controlled fabrication processes to achieve optimal crystalline facets for uniform deposition.
Innovation Solution
The fabrication process involves modifying the trench bottom and sidewalls through crystallographic anisotropic etching to create a recess with controlled facet orientations, allowing for selective epitaxy growth of silicon germanium layers that are flat and uniform, followed by patterning to form GAA devices with tailored nanowire stacks for nFET and pFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to increase drive current, then switching speed is improved, but short-channel effects worsen and compromise current control
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gates that wrap around the channel from all directions (gate-all-around configuration). This dimensional change provides superior electrostatic control over the channel, effectively suppressing short-channel effects while maintaining scaled dimensions for high-speed operation
Solution Approach 2:
The gate structure is designed to surround and enclose the nanowire channel from top, bottom, and sidewalls, creating a nested configuration where the gate completely encompasses the channel region. This provides enhanced electrostatic control compared to conventional partial-gate structures
2Ease of manufacture
If epitaxy layers are grown in trenches with conventional bottom shapes, then deposition process is simplified, but uniformity and crystalline quality of epitaxy layers deteriorate
Solution Approach 1:
Before performing the epitaxy deposition, the patent pre-modes the trench bottom surface through anisotropic etching to create specific crystallographic facet orientations. This preliminary surface preparation ensures that subsequent epitaxy growth proceeds uniformly with high crystalline quality, addressing the root cause of non-uniform deposition
Solution Approach 2:
The patent changes the physical and chemical parameters of the trench bottom surface by controlling the crystallographic orientation of exposed facets through anisotropic etching. By selecting specific facet orientations (such as <110> or <100> planes), the epitaxy process achieves optimal growth conditions for uniform layer formation and high crystalline quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrostatic control of channels, improves device performance by ensuring uniform deposition of epitaxy layers, and facilitates the integration of CMOS processes into high-voltage analog circuits like bipolar-CMOS-DMOS, thereby overcoming short-channel effects.
Implementation Method 1
modifying the trench bottom and sidewalls through crystallographic anisotropic etching to create a recess with controlled facet orientations
Implementation Method 2
selective epitaxy growth of silicon germanium layers that are flat and uniform
Data Source
AI summary
The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.