Gate-All-Around Semiconductor Structure With Enlarged Etching Window
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the incomplete removal of sacrificial layers during the etching process in multi-gate devices, leading to residue formation and unsatisfactory gate structure formation due to densely spaced features and reduced etching windows, which affects device performance.
Innovation Solution
The method involves forming semiconductor fin-shape stacks with alternating channel and sacrificial layers, depositing a hybrid film that can be partially removed during etching, and using a dielectric filler layer and helmet layer to increase the etching window, allowing for the selective removal of sacrificial layers and formation of satisfactory gate structures without damaging adjacent features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching duration is extended to remove sacrificial layers completely, then the sacrificial layer removal is improved, but adjacent features suffer damages
Solution Approach 1:
The patent applies local quality by creating an enlarged etching window specifically at the sacrificial layer region while maintaining the original feature dimensions. The hybrid film structure (first film with higher etch rate, second film with lower etch rate) provides localized etching enhancement only where needed, allowing complete sacrificial layer removal without over-etching adjacent features.
Solution Approach 2:
The etching process is segmented into two distinct stages: a first etching process that removes the sacrificial layer through the enlarged window created by the hybrid film, and a second etching process that forms the gate structure. This segmentation allows precise control over etching depth and prevents damage to adjacent features.
2Productivity
If the feature spacing is reduced to increase device density, then the production efficiency is improved, but the etching window is reduced making sacrificial layer removal difficult
Solution Approach 1:
The patent resolves the etching window constraint by transitioning from a two-dimensional planar structure to a three-dimensional hybrid film structure. The hybrid film extends vertically with varying thickness, creating an enlarged etching window in the vertical dimension while maintaining tight horizontal spacing for high device density.
Solution Approach 2:
The patent changes the etching parameters by introducing a hybrid film structure with differentiated etch rates. The first film layer has a higher etch rate than the second film layer, enabling selective removal of sacrificial material while preserving the underlying channel structure, thus achieving complete removal without requiring larger feature spacing.
3Manufacturing precision
If over-etching is performed to remove residual sacrificial features, then the sacrificial layer removal is improved, but the adjacent features suffer damages
Solution Approach 1:
The patent applies preliminary action by pre-forming the hybrid film structure with an enlarged etching window before the etching process. This pre-prepared structure ensures that the sacrificial layer can be completely removed in the first etching step without requiring subsequent over-etching, thereby preventing damage to adjacent features and maintaining feature integrity.
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a number of channel members over a substrate, a gate structure wrapping around each of the number of channel members, a dielectric fin structure disposed adjacent to the gate structure, the dielectric fin structure includes a first dielectric layer disposed over the substrate and in direct contact with the first gate structure, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer. The third dielectric is disposed over the second dielectric layer and spaced apart from the first dielectric layer and the gate structure by the second dielectric layer. The dielectric fin structure also includes an isolation feature disposed directly over the third dielectric layer.