GAA FET Epitaxial Structure With Air Spacers for Defect Control
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Solution Overview
Problem
The challenge in forming epitaxial source/drain (S/D) regions in gate-all-around (GAA) FETs is the formation of voids and crystal defects due to lattice mismatch and uncontrolled epitaxial growth, which degrades device performance.
Innovation Solution
The use of air spacers and dielectric layers between S/D regions and fin bases limits epitaxial growth to the sidewalls of nanostructured channel regions, preventing growth on fin bases and thus mitigating voids and crystal defects, while back-side contact structures and anchor structures reduce device area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If epitaxial growth is performed on fin bases to form S/D regions, then device area can be reduced, but voids and crystal defects form due to uncontrolled growth
Solution Approach 1:
The patent segments the substrate into distinct regions: fin bases and non-fin bases. Epitaxial growth is selectively performed only on non-fin base regions, while fin bases are protected by air spacers. This segmentation allows S/D region formation without crystal defects by preventing uncontrolled growth on fin bases.
Solution Approach 2:
Air spacers serve as intermediary structures between the fin bases and the epitaxial growth environment. These spacers physically block the epitaxial growth process from occurring on fin bases, acting as a mediator that prevents harmful lattice mismatch and crystal defect formation while allowing growth on intended regions.
2Manufacturing precision
If air spacers and dielectric layers are added to control epitaxial growth, then crystal defects are prevented, but device complexity increases
Solution Approach 1:
The patent extracts the problematic epitaxial growth process from the fin base regions by removing the growth capability selectively. Air spacers are used to take out or eliminate the growth reaction on fin bases, leaving only the desired growth on non-fin base regions. This extraction approach simplifies the overall structure by avoiding the need for complex masking or protection schemes.
3Area of moving object
If back-side contact structures are implemented to reduce device area, then power consumption decreases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions the contact structure arrangement from a planar (2D) configuration to a three-dimensional configuration by implementing back-side contacts. This dimensional change allows contacts to be formed on the substrate back surface, reducing the front-side device area and enabling better space utilization without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the formation of voids and crystal defects in S/D regions, enhancing the performance of GAA FETs and reducing power consumption by minimizing device area and interconnects.
Implementation Method 1
The use of air spacers and dielectric layers between S/D regions and fin bases limits epitaxial growth to the sidewalls of nanostructured channel regions
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, a stack of nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, an air spacer disposed between the S/D region and the fin base, and a dielectric layer disposed between the air spacer and the fin base.