Backside Isolation Module for GAA FET Contact Separation
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Solution Overview
Problem
Backside power delivery in semiconductor devices poses challenges in patterning electrical contact features isolated from one another by isolation modules within tight spaces without impacting the performance of transistors on the front side of the chip.
Innovation Solution
The method involves forming placeholders interfacing with extension regions via a cap layer in recesses isolated by shallow trench isolations, followed by selective deposition, isotropic etching, conformal deposition, spacer sculpting, cap layer removal, and contact metallization to form metal contacts isolated by an inter-layer dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If backside power delivery is implemented to eliminate front side interconnect sharing, then power delivery efficiency is improved, but patterning electrical contact features in tight spaces becomes more difficult
Solution Approach 1:
The patent divides the contact formation process into multiple stages using placeholders that are formed, removed, and replaced with selective cap layers. This segmentation allows the complex patterning task to be broken down into manageable steps that can be performed with standard equipment, resolving the contradiction between achieving efficient backside power delivery and maintaining ease of manufacture.
Solution Approach 2:
The patent performs preliminary actions by forming placeholders and selective cap layers before final contact patterning. These preliminary structures guide subsequent etching and deposition processes, enabling precise contact formation in tight spaces without requiring advanced patterning capabilities, thus maintaining ease of manufacture while achieving efficient power delivery.
2Productivity
If electrical contact features are patterned in tight spaces on backside, then backside power delivery is achieved, but extension regions on front side may be impacted
Solution Approach 1:
The patent uses placeholders and selective cap layers as intermediary structures that mediate between the backside contact patterning process and the front side extension regions. These intermediaries protect the extension regions from damage during backside processing while still allowing the desired contact features to be formed, thus maintaining transistor performance while achieving backside power delivery capability.
Solution Approach 2:
The patent applies preliminary anti-action by forming protective cap layers over extension regions before performing backside etching processes. This protective action prevents potential damage to the extension regions during contact formation, ensuring transistor performance is maintained while enabling backside power delivery to be implemented.
3Manufacturing precision
If multiple processing steps are performed for contact formation, then contact precision is improved, but process complexity increases
Solution Approach 1:
The patent employs universal processing steps such as conformal deposition, isotropic etching, and spacer formation that can be applied repeatedly with consistent parameters. These multi-functional processes achieve high contact precision without requiring specialized equipment or highly complex process sequences, thus improving manufacturing precision while limiting the increase in process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of metal contacts isolated from one another on the backside of a chip while protecting extension regions on the front side, effectively addressing the challenges of backside power delivery.
Implementation Method 1
performing a substrate removal process to isotropically etch the substrate within the recesses
Implementation Method 2
performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses
Data Source
AI summary
A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.