GAA FET SiGe Source/Drain Stack for Lateral Etch Control
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Solution Overview
Problem
In semiconductor manufacturing, particularly for GAA FETs, controlling lateral etching during the release of nanostructures is challenging, leading to issues with gate-to-drain capacitance and the formation of defect-free source/drain epitaxial layers, which affects device performance.
Innovation Solution
A novel method for fabricating source/drain epitaxial layers involves forming a base epitaxial layer and multiple epitaxial layers with varying compositions, using techniques like CVD and MBE, to ensure precise control and defect-free formation, with a non-doped base layer to suppress voids and improve short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to release nanostructures, then the manufacturing process is simple, but lateral etching cannot be controlled, leading to increased gate-to-drain capacitance and device performance degradation
Solution Approach 1:
The etching process is segmented into multiple selective etching steps with different etchants. First, a sacrificial layer is etched away, then the nanostructures are released through a second etching step. This segmentation allows control over lateral etching at each stage rather than uncontrolled single-step etching.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary element that enables controlled release of nanostructures. The sacrificial layer is selectively etched first, creating space for nanostructure release while preventing direct uncontrolled etching of the nanostructures themselves, thus controlling lateral etching effects.
2Reliability
If source/drain epitaxial layers are formed without a base layer, then the formation process is simpler, but voids and defects occur, affecting device reliability
Solution Approach 1:
A base layer is formed preliminarily before depositing the source and drain epitaxial layers. This preliminary base layer provides a foundation that prevents void formation and defects during subsequent epitaxial growth, ensuring defect-free final structures.
Solution Approach 2:
The epitaxial layer structure is made non-uniform with different regions having different compositions and doping levels. The base layer has specific properties tailored for defect prevention, while subsequent layers have properties optimized for electrical performance, creating local quality variations that solve different problems in different regions.
3Manufacturing precision
If gate structures are formed before nanostructure release, then the manufacturing sequence is simplified, but gate-to-drain capacitance increases due to uncontrolled lateral etching
Solution Approach 1:
The manufacturing sequence is made dynamic and adaptive rather than fixed. The gate structure formation is integrated with the nanostructure release process through selective etching steps, allowing the process to adapt to the specific requirements of each structure type and minimizing unnecessary waiting time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control over lateral etching, reduces gate-to-drain capacitance, and ensures defect-free source/drain epitaxial layers, thereby improving the performance and reliability of GAA FETs.
Implementation Method 1
using techniques like CVD and MBE
Implementation Method 2
using techniques like CVD and MBE
Data Source
AI summary
A semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.