GAA FET Gate Stack for Threshold Voltage Modulation
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Solution Overview
Problem
Conventional methods for modulating threshold voltages in MOSFETs are incompatible with gate-all-around FET architectures, particularly at sub 10-15 nm technology nodes, necessitating new systems and methods for forming gate stack structures with modulated threshold voltages.
Innovation Solution
The method involves forming a dipole metal layer on a high-κ gate dielectric layer, annealing, and removing it, as well as creating p-type and n-type work function adjusting layers using doped conductive materials, integrated with a high-κ gate dielectric and metal gate electrode to modulate threshold voltages in gate-all-around FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional Vt modulation methods (interface dipole layer or work function adjusting layer) are used in MOSFETs, then threshold voltage can be modulated, but the method is incompatible with gate-all-around FET architecture at sub 10-15 nm nodes
Solution Approach 1:
The patent transitions from planar Vt modulation methods to a three-dimensional approach by forming a dipole layer within the high-k gate dielectric layer itself. This allows the dipole layer to be positioned at the interface between the gate dielectric and the channel in the GAA FET structure, enabling effective Vt modulation while maintaining compatibility with the vertical gate-all-around architecture.
Solution Approach 2:
The patent introduces a dipole layer as an intermediary element formed within the high-k gate dielectric. This dipole layer serves as a mediator that modulates the threshold voltage by creating an electric dipole moment at the gate dielectric-channel interface, enabling Vt control without requiring separate interface dipole layers or work function adjusting layers that are incompatible with GAA FETs.
2Reliability
If dipole metal layer is formed and annealed to create dopants in high-k gate dielectric, then threshold voltage modulation is achieved, but additional process steps are required
Solution Approach 1:
The patent combines multiple functions into a single dipole metal layer formation and annealing process. This process simultaneously creates the dipole layer within the high-k gate dielectric, introduces dopants to modulate threshold voltage, and forms the necessary interface structure, thereby reducing the number of separate process steps compared to conventional methods.
Solution Approach 2:
The patent utilizes parameter changes during the annealing process of the dipole metal layer. By controlling annealing temperature and duration, dopants are selectively activated and distributed within the high-k gate dielectric, achieving the desired threshold voltage modulation while managing the complexity of the fabrication process through precise parameter control.
3Adaptability or versatility
If p-type and n-type work function adjusting layers are formed with doped conductive material, then multi-Vt optimization is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming p-type and n-type work function adjusting layers with doped conductive materials in specific regions of the gate electrode. This allows different threshold voltages to be achieved in different device regions or device types (e.g., PMOS and NMOS) within the same integrated circuit, enabling multi-Vt optimization while maintaining compatibility with GAA FET architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of gate stack structures with controllable threshold voltages, suitable for extremely scaled process nodes, optimizing power consumption and performance in GAA FETs.
Implementation Method 1
annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.
Implementation Method 2
forming a p-type work function adjusting layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, forming an n-type work function adjusting layer on the high-κ gate dielectric layer. The p-type work function adjusting layer comprises p-doped conductive material, and the n-type work function adjusting layer comprises n-doped conductive material.
Data Source
AI summary
A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.