GAA FET Epitaxial S/D Structure With Ge Liner Seeding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in forming epitaxial source/drain (S/D) regions in gate-all-around (GAA) FETs is the difficulty in controlling the direction and location of epitaxial growth, leading to voids and crystal defects, which degrade device performance. Additionally, the high concentration of germanium in p-type S/D regions can result in high parasitic resistances and capacitances, as well as drain-induced barrier lowering (DIBL) effects.

Innovation Solution

The solution involves forming epitaxial p-type S/D regions with a Ge-based epitaxial region and epitaxial liners along the sidewalls of the nanostructured channel regions and inner spacers. The epitaxial liners act as a continuous seeding layer for the epitaxial growth of the Ge-based region, improving growth quality and preventing contact with inner spacers, thus reducing parasitic effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If epitaxial growth is performed to form p-type S/D regions with high germanium concentration, then device performance is improved, but parasitic resistances and capacitances increase

Engineering Contradiction:
Improvedevice performanceVSAvoidparasitic resistances and capacitances
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The S/D region is divided into multiple epitaxial layers with different germanium concentrations. The lower germanium concentration layer is positioned closer to the channel to minimize parasitic effects, while the higher germanium concentration layer is positioned further away to provide the performance benefits. This segmentation allows optimization of both device performance and parasitic reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the S/D structure are assigned different germanium concentrations based on their functional requirements. The region adjacent to the channel has lower germanium concentration to reduce parasitic resistances and capacitances, while regions further from the channel have higher germanium concentration to enhance device performance. This local quality variation resolves the contradiction between performance improvement and parasitic reduction.

Inventive Principle:
Principle #3Local quality

2Reliability

If epitaxial growth is performed to form Ge-based epitaxial region, then device performance is improved, but voids and crystal defects are formed

Engineering Contradiction:
Improvedevice performanceVSAvoidgrowth quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

An undoped silicon epitaxial layer is formed as a preliminary layer before depositing the germanium-containing epitaxial layers. This preliminary undoped layer serves as a buffer that prevents void formation and crystal defects during subsequent germanium epitaxial growth, while still allowing the high-performance Ge-based regions to be formed. The preliminary action resolves the contradiction between achieving high device performance and maintaining growth quality.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the epitaxial growth quality of the p-type S/D regions, reducing defects and improving performance. It also minimizes parasitic resistances, capacitances, and DIBL effects, leading to better overall performance of GAA FETs.

Implementation Method 1

The epitaxial liners act as a continuous seeding layer for the epitaxial growth of the Ge-based region, improving growth quality

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20250081557A1Epitaxial structures in semiconductor devices
Publication Date: 2025.03.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250081557A1 patent drawing
  • US20250081557A1 patent drawing
  • US20250081557A1 patent drawing

AI summary

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.