GAA FET Inner Spacer Design for Lateral Etching Control
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Solution Overview
Problem
In the manufacturing of gate-all-around (GAA) FETs, controlling lateral etching during the release of nanowires is challenging due to insufficient etching control, leading to issues with gate-to-drain capacitance and uniformity of inner spacers, which affects gate control and increases channel resistance.
Innovation Solution
A novel method is introduced where an inner spacer with a recessed cross-sectional shape is formed between the metal gate electrode and the source/drain epitaxial layer, allowing for improved gate control and reducing channel resistance by providing more space for the gate dielectric layer and electrode, thus enhancing the uniformity and precision of the GAA FET structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to release nanowires, then the nanowire structure can be formed, but lateral etching control is insufficient leading to poor gate-to-drain capacitance control and non-uniform inner spacers
Solution Approach 1:
A dummy gate structure is formed prior to nanowire release etching to serve as a protective mask. This preliminary structure prevents lateral etching from reaching the source/drain regions, thereby controlling gate-to-drain capacitance and ensuring uniform inner spacer formation during the subsequent release process
Solution Approach 2:
The dummy gate structure acts as an intermediary protective layer between the etching process and the actual gate structure. It absorbs the lateral etching attack, protecting the source/drain regions and enabling precise control of the release process without directly participating in the final device operation
2Reliability
If the gate structure is positioned closer to the source/drain region, then gate control is improved, but channel resistance increases due to insufficient space for gate dielectric layer and electrode
Solution Approach 1:
The inner spacer extends in the vertical dimension beneath the gate electrode, providing additional separation between the gate and source/drain regions without increasing the lateral footprint. This vertical spacing allows the gate to be positioned closer laterally for improved control while maintaining adequate dielectric spacing to prevent shorting and reduce channel resistance
3Productivity
If larger wafer sizes are used for manufacturing, then productivity is improved, but process uniformity deteriorates
Solution Approach 1:
The dummy gate structure provides self-aligned protection during the release etching process. By being formed in the same patterning step as the actual gate, it automatically ensures uniform spacing and protection across the entire wafer surface, maintaining process uniformity even as wafer size increases and enabling higher productivity
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.