Stacked GAA-FET Channel Structure With Inner Spacer Isolation
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Solution Overview
Problem
Manufacturing GAA-FET devices with channels of tens of nanometers or less thickness is challenging due to structural stress and dislocation issues, which affects performance and increases leakage current.
Innovation Solution
A low-temperature recurring cooling process is employed to grow silicon germanium and silicon layers, reducing stress and enabling defect-free single crystal silicon layer stacking, along with forming an inner spacer using thermal oxidation to support the channel structure and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If channels having a thickness of tens nm or less are stacked to form GAA-FET structure, then the contact area between gate and channel increases and current driving capability is improved, but structural stress and dislocation issues occur affecting manufacturing precision
Solution Approach 1:
The channel structure is segmented into multiple thin silicon layers (e.g., 3-7 layers) stacked vertically, each with thickness of tens of nanometers. This segmentation allows the total channel thickness to be controlled precisely while maintaining uniformity through individual layer formation processes, resolving the contradiction between increasing contact area and maintaining manufacturing precision.
Solution Approach 2:
The invention transitions from planar channel structure to three-dimensional stacked channel structure. By stacking multiple thin silicon layers vertically, the gate can surround all surfaces of each channel layer, dramatically increasing the gate-channel contact area while maintaining precise control over each layer's thickness through vertical stacking rather than lateral expansion.
2Productivity
If multiple silicon layers are stacked to increase channel contact area, then productivity and current driving capability are enhanced, but leakage current increases due to structural defects
Solution Approach 1:
The invention changes the material composition parameter by forming alternating layers of silicon and silicon germanium. The silicon germanium layers serve as sacrificial layers that are selectively removed, while the silicon layers form the functional channels. This parameter change enables precise control over channel quality and reduces leakage current while maintaining high productivity through the stacked structure.
Solution Approach 2:
Different material qualities are applied locally: silicon layers provide high-quality low-defect channels for current conduction, while silicon germanium layers provide etch-selective sacrificial structures. This local differentiation of material quality allows the stacked structure to achieve both high productivity and low leakage current by ensuring each layer serves its optimal function.
3Ease of manufacture
If conventional high-temperature processes are used to grow silicon layers, then layer formation is achieved, but structural stress and dislocation occur reducing manufacturing precision
Solution Approach 1:
The invention changes the temperature parameter from conventional high-temperature processes to low-temperature processes (e.g., below 700°C) for growing silicon and silicon germanium layers. This parameter change reduces thermal stress and dislocation formation during layer formation, enabling precise control over channel thickness while maintaining ease of manufacture through standard low-temperature epitaxial growth techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances driving current and reduces leakage current by increasing the number of silicon layer stacks and allowing precise channel length adjustment, while preventing short circuits between the gate electrode and source/drain.
Implementation Method 1
forming alternating layers, where a silicon germanium layer and a silicon layer are alternately stacked, on a substrate
Implementation Method 2
forming an inner spacer using thermal oxidation to support the channel structure and prevent short circuits
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes forming alternating layers, where a silicon germanium layer and a silicon layer are alternately stacked, on a substrate, etching the alternating layers to form a fin structure protruding onto the substrate and then forming a silicon nitride film on a surface and a sidewall of each of the alternating layers having the fin structure, sequentially forming a dummy gate and a silicon oxide film on the alternating layers with the silicon nitride film therebetween and then forming a gate spacer on a sidewall of the dummy gate, etching the silicon nitride film upward exposed, and then, etching the alternating layers by using the silicon oxide film, and selectively forming an inner spacer in a sidewall of each of silicon germanium layers among the silicon germanium layers and silicon layers of the etched alternating layers.