GAA FET Inner Spacer Narrowing for Lower Gate Capacitance
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Solution Overview
Problem
As semiconductor technology advances to sub-20-25 nm nodes, gate-all-around FETs require further improvements to reduce capacitance and enhance DC performance, particularly in the inner spacers between the gate electrodes and source/drain regions.
Innovation Solution
The width of inner spacers between the gate electrode and the source/drain regions of a GAA FET is reduced, optimizing the capacitance and improving DC performance by altering the materials and processes used in the manufacturing process, including the use of epitaxial growth and selective etching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of inner spacers is reduced to reduce capacitance, then DC performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material composition of inner spacers by incorporating silicon germanium (SiGe) with varying germanium concentrations (e.g., 20-80 at%). This material parameter change enables precise control of spacer width through selective etching processes while maintaining the required narrow dimensions for reduced capacitance. The varying Ge concentration creates etch selectivity that facilitates precise width control during manufacturing.
Solution Approach 2:
The patent applies different materials with different germanium concentrations to different regions of the inner spacers. By creating a gradient or varying composition within the spacer structure, the patent achieves localized properties that enable precise width control in critical areas while maintaining structural integrity elsewhere. This local differentiation allows for refined manufacturing control.
2Reliability
If epitaxial growth and selective etching are used to reduce inner spacer width, then capacitance is reduced, but process complexity increases
Solution Approach 1:
The patent incorporates silicon germanium layers during the initial epitaxial growth stage, preparing the structure in advance for subsequent selective etching. By pre-configuring the material composition with varying Ge concentrations in the inner spacers, the patent enables the later selective removal process to precisely achieve the desired narrow width without requiring complex real-time adjustments. This preliminary material preparation simplifies the overall process despite adding an epitaxial growth step.
Solution Approach 2:
The patent uses composite material structures with silicon germanium layers having different germanium concentrations integrated into the inner spacer regions. This composite approach allows selective etching to differentiate between spacer regions and remove material precisely, achieving narrow widths through material composition differences rather than purely geometric control. The composite structure enables the complex outcome with a systematic material-based approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the DC performance of GAA FET devices by reducing capacitance, thereby improving operational efficiency and effectiveness.
Implementation Method 1
alternately formed thereon a plurality of first semiconductor layers 20 and second semiconductor layers 25 made of different materials having different lattice constants
Implementation Method 2
The remaining portions of the sacrificial semiconductor layers are removed to release a plurality of semiconductor layers formed of the non-sacrificial semiconductor material
Data Source
AI summary
Manufacturing method of semiconductor device includes forming first and second multilayer stacks over a substrate. First and second multilayer stacks include plurality of spaced apart nanosheets arranged along first direction of stack, and dielectric spacers disposed between adjacent nanosheets. A mask layer is formed over first and second multilayer stacks. A first portion of mask layer over first multilayer stack is removed to expose plurality of nanosheets and dielectric spacers of first multilayer stack. A portion of the dielectric spacers of first multilayer stack along second direction perpendicular to first direction of stack is removed to decrease thickness of dielectric spacers of first multilayer stack along second direction. A second portion of the mask layer over second multilayer stack is removed to expose plurality of nanosheets and dielectric spacers of second multilayer stack, and gate structures are wrapped around plurality of nanosheets of first and second multilayer stacks.