GAA FET Leakage Reduction via Insulated Source-Drain Isolation
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Solution Overview
Problem
The development of gate-all-around field effect transistors (GAA FETs) faces challenges with off-state leakage current, particularly when using narrow-band gap materials like Ge as channel material, due to the presence of parasitic transistors caused by sacrificial layers in the manufacturing process.
Innovation Solution
The manufacturing process involves forming fin structures with an insulating material layer between the source/drain regions and the substrate, preventing the formation of parasitic transistors and reducing off-state leakage current by using a different insulating material than the ILD and isolation layers, and removing the sacrificial layer to create a semiconductor wire structure with a gate dielectric and electrode layer wrapping around the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If narrow-band gap materials like Ge are used as channel material in GAA FETs, then device performance is improved, but off-state leakage current increases due to parasitic transistors formed by sacrificial layers
Solution Approach 1:
The sacrificial layer (first semiconductor layer) is completely removed from the structure after forming the semiconductor wire and gate wrap-around structure. This extraction eliminates the parasitic transistor formation at the interface between the sacrificial layer and substrate, thereby reducing off-state leakage current while maintaining the performance benefits of narrow-band gap channel materials.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the bottom portion of the fin structure and the substrate. This insulating layer prevents direct contact and electrical interaction that would form parasitic transistors, effectively blocking the harmful leakage current path while allowing the beneficial narrow-band gap channel material to maintain its performance.
2Ease of manufacture
If sacrificial layers are used in the manufacturing process of GAA FETs, then the gate wrap-around structure can be formed, but parasitic transistors are created causing off-state leakage
Solution Approach 1:
The sacrificial layer serves its manufacturing purpose of enabling gate wrap-around formation, then is completely removed afterward. This temporary use followed by extraction allows the structure to be manufactured easily while eliminating the source of parasitic transistors that would otherwise persist in the final device.
Solution Approach 2:
The sacrificial layer is discarded after completing its temporary function as a structural support during manufacturing. Its removal recovers the structure from a state with parasitic transistors to a clean state without them, while the gate wrap-around structure remains intact.
3Ease of manufacture
If source/drain regions are directly connected to the substrate, then manufacturing is simplified, but parasitic transistors form increasing off-state leakage current
Solution Approach 1:
An insulating layer is placed between the source/drain regions (bottom portion of fin structure) and the substrate. This intermediary prevents direct electrical connection that would create parasitic transistors, blocking the leakage current path while maintaining structural integrity and manufacturability.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.