GAA FET Gate Structure With Insulating Layer for Leakage Control
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Solution Overview
Problem
As semiconductor technology advances to nanometer process nodes, gate-all-around (GAA) FETs face challenges in reducing leakage current and minimizing parasitic PN junctions due to the lack of gate control over the bottom surface of the channel region, which affects the ION/IOFF ratio.
Innovation Solution
Incorporating an insulating layer between the bottommost gate structure and the underlying semiconductor substrate in GAA FETs to reduce leakage current and minimize parasitic PN junctions, while improving the ION/IOFF ratio by ensuring fuller depletion in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around (GAA) FET structure is used to surround the channel region on all sides, then fuller depletion in the channel region is achieved resulting in less short-channel effects, but leakage current is not sufficiently reduced due to lack of gate control over the bottom surface
Solution Approach 1:
An insulating layer is introduced as an intermediary element between the bottommost gate structure and the underlying semiconductor substrate. This insulating layer acts as a mediator that blocks the parasitic PN junction formation and leakage current paths while maintaining the electrical isolation needed for proper device operation, thereby reducing leakage current without adding complex gate control mechanisms
Solution Approach 2:
The gate structure is segmented into multiple levels with different functions: upper gate structures provide control over the channel region, while the lower insulating layer provides electrical isolation from the substrate. This segmentation allows the gate structure to fulfill multiple functions - channel control and leakage prevention - without requiring a single complex gate design
2Productivity
If the gate structure is positioned closer to the channel region to improve control, then switching performance is enhanced, but parasitic PN junctions increase affecting the ION/IOFF ratio
Solution Approach 1:
The insulating layer serves as an intermediary that physically separates the gate structure from direct contact with the semiconductor substrate, thereby eliminating parasitic PN junction formation. This allows the gate to be positioned close to the channel for improved control without the harmful side effect of parasitic junctions
Solution Approach 2:
The harmful parasitic PN junction effect is extracted or removed from the device structure by introducing the insulating layer. This layer takes out the unwanted electrical interaction between the gate and substrate, allowing the beneficial close-proximity gate control to function without parasitic contamination
Data Source
AI summary
An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.