Dual-Layer Isolation in GAA FETs for Lower Gate Capacitance
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Solution Overview
Problem
The increased gate-to-source/drain capacitance in advanced technology nodes due to larger metal gate endcaps and source/drain epitaxy sizes in gate-all-around transistors leads to higher capacitance and reduced performance.
Innovation Solution
Implementing a dielectric structure between adjacent channel stacks and replacing the gate metal with dielectric material to reduce the area facing source/drain contact metals, and using a dielectric helmet structure above the channels to minimize gate metal exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate-all-around transistor structure with larger metal gate endcaps and source/drain epitaxy sizes is used, then transistor drive current and scaling are improved, but gate-to-source/drain capacitance increases
Solution Approach 1:
The patent extracts and removes the metal gate material from the endcap regions between adjacent transistors, replacing it with dielectric material. This extraction eliminates the capacitive coupling between metal gate endcaps and source/drain regions, directly reducing the harmful gate-to-source/drain capacitance while preserving the gate-all-around structure's drive current capabilities
Solution Approach 2:
The patent introduces dielectric material as an intermediary between the gate structure and source/drain regions. This dielectric intermediary layer (such as silicon oxide or silicon nitride) acts as an insulating barrier that reduces direct capacitive coupling, thereby lowering gate-to-source/drain capacitance while allowing the transistor to maintain its scaling and drive current performance
2Power
If metal gate endcap area is increased to improve transistor performance, then drive current is enhanced, but gate capacitance and signal interference increase
Solution Approach 1:
The patent selectively removes metal gate material from the endcap regions, extracting only the portion that contributes to harmful capacitance. This partial extraction maintains sufficient gate coverage for drive current while eliminating the capacitive burden of large metal endcaps
Solution Approach 2:
The patent applies different material compositions to different regions of the gate structure. The gate material is maintained in channel regions for effective control but replaced with dielectric material in endcap regions to reduce capacitance, creating local quality variations that optimize both drive current and capacitance characteristics
Data Source
AI summary
An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.