Asymmetric GAA FET Isolation for Low-Leakage Analog Gain
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Solution Overview
Problem
Existing nanostructure FET devices face challenges in isolating the nanostructure FET devices from the underlying semiconductor substrate, leading to unwanted current leakage and parasitic capacitance, which limits their application in analog circuits due to the need for an insulating layer that restricts the formation of a p-n junction.
Innovation Solution
A gate-all-around (GAA) FET device is designed with an asymmetrical configuration where the drain structure is electrically isolated from the semiconductor substrate using a dielectric layer, while the source structure is coupled to the substrate through a semiconductor well, forming a p-n junction, thereby reducing leakage current and enhancing the intrinsic gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an insulating layer is used to isolate the nanostructure FET device from the semiconductor substrate, then current leakage is reduced, but the formation of a p-n junction is restricted
Solution Approach 1:
The patent applies different isolation strategies to different regions: the drain structure is isolated from the substrate using a dielectric layer to reduce leakage, while the source structure is directly coupled to the substrate to enable p-n junction formation. This local differentiation resolves the contradiction by allowing both leakage reduction and p-n junction formation in appropriate locations.
Solution Approach 2:
The patent segments the isolation approach by dividing the device into source and drain regions with different isolation configurations. The drain is isolated while the source is not, creating distinct functional zones that simultaneously achieve low leakage and enable plasma charge release through the source-substrate p-n junction.
2Object-affected harmful factors
If the nanostructure FET device is isolated from the semiconductor substrate, then parasitic capacitance is reduced, but the device complexity increases
Solution Approach 1:
The patent reduces parasitic capacitance by applying isolation only where needed (under the drain structure) rather than uniformly across the entire device. This localized approach minimizes the capacitive coupling between the channel and substrate while avoiding the complexity of complete device isolation.
Solution Approach 2:
Instead of isolating the entire device from the substrate, the patent inverts the approach by allowing direct contact in critical regions (source to substrate) while isolating only specific areas (drain). This inversion enables the device to benefit from both isolation (reduced parasitic capacitance) and direct coupling (simplified structure in source region).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces leakage current and allows for increased intrinsic gain, making the GAA FET device suitable for various analog-related applications by enabling the formation of a p-n junction necessary for plasma charge release.
Implementation Method 1
the drain structure is electrically isolated from the semiconductor substrate using a dielectric layer
Implementation Method 2
the source structure is coupled to the substrate through a semiconductor well, forming a p-n junction, thereby reducing leakage current and enhancing the intrinsic gain
Data Source
AI summary
A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.