GAA FET Isolation Structure Protection Against Over-Etching
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Solution Overview
Problem
Isolation structures in gate-all-around field-effect transistors (GAA FETs) are vulnerable to dry etching and wet cleaning processes, leading to over-etching and excessive junction leakage.
Innovation Solution
A method of forming isolation structures for GAA FETs involves depositing dielectric layers over the isolation structure and fins, followed by selective etching to retain these layers only on the top surface of the isolation structure, thereby protecting it from subsequent etching processes and reducing junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If isolation structures are formed with silicon oxide deposited using flowable CVD, then the isolation structures can be formed in GAA FETs, but the isolation structures become vulnerable to dry etching and wet cleaning processes, leading to over-etching and excessive junction leakage
Solution Approach 1:
A protective dielectric layer is deposited over the isolation structure before subsequent etching and cleaning processes. This preliminary protective action prevents the isolation structure from being damaged by over-etching in later processing steps, thereby reducing junction leakage while maintaining ease of manufacture
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the isolation structure and the harmful etching/cleaning processes. This intermediary layer protects the isolation structure from direct exposure to damaging processes, resolving the contradiction between manufacturability and reliability
2Productivity
If dry etching and wet cleaning processes are used frequently in forming GAA FETs, then the fabrication process can be completed, but the isolation structures are over-etched, leading to excessive junction leakage
Solution Approach 1:
The protective dielectric layer is deposited in advance before the frequent dry etching and wet cleaning steps. This allows the fabrication process to proceed efficiently with multiple cleaning and etching steps while the protective layer prevents damage to the isolation structure, maintaining both productivity and precision
Solution Approach 2:
The dielectric layer serves as a cushioning protective layer that absorbs the harmful effects of frequent etching and cleaning processes. This beforehand protection allows aggressive process conditions to be used for productivity without compromising isolation structure integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively mitigates junction leakage by preserving the isolation structure, ensuring the integrity of the GAA FETs during fabrication, thereby enhancing the reliability and performance of the semiconductor device.
Implementation Method 1
isolation structures (e.g., shallow trench isolation or STI) in GAA FETs may be formed with silicon oxide deposited using flowable chemical vapor deposition (CVD)
Data Source
AI summary
A method includes providing a structure having a substrate, fins and an isolation structure over the substrate, wherein each fin includes first and second semiconductor layers alternatingly stacked. The method further includes depositing a first dielectric layer over top and sidewalls of the fins and over a top surface of the isolation structure; depositing a second dielectric layer over the first dielectric layer; and etching back the first and the second dielectric layers such that they remain on the top surface of the isolation structure and are removed from the top and sidewalls of the fins. The method further includes forming dummy gate stacks, gate spacers, source and drain trenches, and inner spacers, wherein the first and the second dielectric layers remain on the top surface of the isolation structure.