GAA FET Channel Layer Composition for Precise Lateral Etching
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Solution Overview
Problem
In the fabrication of gate-all-around (GAA) FETs, controlling lateral etching of nanowires and forming uniform inner spacers is challenging due to insufficient etching control, leading to issues with gate control capability and increased channel resistance, particularly as transistor dimensions shrink to sub-10-15 nm technology nodes.
Innovation Solution
The method involves using sacrificial semiconductor layers with modulated Ge concentration to control the dimension of channel regions, allowing for improved gate control by adjusting the Ge concentration in the first semiconductor layers, which affects the etching rates and enables more precise control over the channel height and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching control methods are used in GAA FET fabrication, then the fabrication process is simple, but lateral etching control of nanowires is insufficient leading to poor gate control capability and increased channel resistance
Solution Approach 1:
The patent applies parameter changes by modulating the Ge concentration in sacrificial semiconductor layers. Different Ge concentrations (e.g., 0-30% in first layers, 40-70% in second layers) create controlled etching rate differences, enabling precise lateral etching control and uniform inner spacer formation without increasing overall process complexity
Solution Approach 2:
The patent implements local quality by creating spatial variations in Ge concentration within the semiconductor layers. The first semiconductor layers have lower Ge concentration while second layers have higher Ge concentration, allowing different regions to etch at different rates and achieve uniform channel dimensions
2Productivity
If transistor dimensions are scaled down to sub-10-15 nm nodes, then device density and performance improve, but gate control capability deteriorates due to insufficient channel region control
Solution Approach 1:
The patent uses parameter changes by adjusting Ge concentration in sacrificial layers to control etching rates, enabling precise channel height and width control at sub-10-15 nm nodes, thereby maintaining gate control capability despite dimensional scaling
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor structure into multiple layers with different Ge concentrations (first layers with 0-30% Ge, second layers with 40-70% Ge). This segmentation allows independent control of etching rates in different regions, achieving uniform channel dimensions at scaled dimensions
3Manufacturing precision
If uniform inner spacers are formed in GAA FET structure, then gate control capability improves, but etching control difficulty increases
Solution Approach 1:
The patent resolves etching control difficulty by changing the Ge concentration parameter in sacrificial layers. The modulated Ge concentration creates controlled etching rate differences that naturally produce uniform inner spacers, transforming a difficult etching control problem into a material composition control problem
Solution Approach 2:
The patent uses sacrificial semiconductor layers with specific Ge concentrations as intermediaries. These layers mediate the etching process by providing controlled etching rates that enable uniform inner spacer formation, simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control capability and achieves uniformity in the GAA FET structure, improving the fabrication process and reducing channel resistance, especially on larger 12-inch wafers, by modulating the Ge concentration in the semiconductor layers to control etching rates and channel dimensions.
Implementation Method 1
At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers. In one embodiment, a Ge concentration of the first semiconductor layers decreases from a bottom one to a top one of the first semiconductor layers.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.