GAA FET Source/Drain Isolation Structure for Leakage Control
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Solution Overview
Problem
As semiconductor technology advances to nanometer process nodes, FinFETs and GAA FETs face challenges in reducing leakage current, particularly due to the diffusion of anti-punch through (APT) impurities into the channel region, which degrades transistor performance.
Innovation Solution
The proposed solution involves manufacturing a GAA FET with a unique groove structure in the fin structure, where a dielectric layer is inserted between the source/drain epitaxial layer and the fin structure, and the groove is formed through multiple dry and wet etching operations to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-punch through (APT) impurities are introduced to reduce leakage current, then off-state leakage is reduced, but APT impurities diffuse into the channel region degrading transistor performance
Solution Approach 1:
A dielectric layer is introduced as an intermediary barrier between the source/drain epitaxial layer (containing APT impurities) and the fin structure (channel region). This dielectric layer prevents APT impurity diffusion into the channel while allowing the APT treatment to proceed in the source/drain regions, thus resolving the contradiction between reducing leakage and maintaining channel purity
Solution Approach 2:
The source/drain region is segmented into two parts: the epitaxial layer containing APT impurities for leakage reduction, and the channel region protected by the dielectric layer to maintain purity. This segmentation allows different regions to have different impurity concentrations, achieving both leakage reduction and performance maintenance
2Reliability
If multiple etching operations are performed to form the groove structure, then leakage current is reduced through better APT dose control, but manufacturing process complexity increases
Solution Approach 1:
The groove structure is formed preliminarily in the fin structure before source/drain epitaxial layer formation. This preliminary action allows subsequent APT treatment and dielectric layer deposition to proceed more efficiently, reducing the need for multiple corrective etching operations and simplifying the overall process
Solution Approach 2:
The groove structure creates local quality variations in the fin structure, with different regions having different depths and exposures. This allows selective APT treatment and dielectric layer formation in specific areas, achieving leakage reduction without requiring complex global process modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces off-state leakage current by minimizing the APT dose and simplifies the process of forming inner spacers, thereby enhancing transistor performance and manufacturing efficiency.
Implementation Method 1
the groove is formed through multiple dry and wet etching operations
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.